Marcus,
thanks for your reply, the different build generate exactly the same
binaries which just
not the same with the binary in uhd git repo.
On Thu, Sep 15, 2011 at 9:37 AM, Marcus D. Leech wrote:
> **
> On 14/09/11 09:31 PM, Page Jack wrote:
>
> Why no one have the answer or have the same que
On 14/09/11 09:31 PM, Page Jack wrote:
> Why no one have the answer or have the same question?
99.9% of the people on this list have no experience building the
firmware or making
modifications to it, they just use the as-supplied firmware.
The way the fpga code is setup, it's intended to be buil
Why no one have the answer or have the same question?
On Fri, Aug 12, 2011 at 9:52 AM, Page Jack wrote:
> Hi all,
> I have some problems when compile the fpga source.
> I open uhd-git\fpga\usrp1\toplevel\usrp_std\usrp_std.qpf with quartus II
> then compile meet a lot of errors which is the path
Hi all,
I have some problems when compile the fpga source.
I open uhd-git\fpga\usrp1\toplevel\usrp_std\usrp_std.qpf with quartus II
then compile meet a lot of errors which is the path error like that:
Error (10054): Verilog HDL File I/O error at rx_buffer.v(25): can't open
Verilog Design File "../.
