seph 004 wrote:
This would mean that to obtain a total rate of 32 Msamples/sec to the
DAC, the data rate of the I and Q channels would have to be 16
Msamples/sec each, and thus 128 000 samples/sec each into the txchain
modules. This should mean that if I provide a samples set of 128 I
samples
I've managed to store a sample set on the FPGA and transmit it periodically.
The problem I'm experiencing is that the transmitted pulse is shorter than what
I expected.
I worked out that by setting an interp value of 500 from python, that the FPGA
interpolator would basically be set to 125 to g
