Hi Firas,
yes, it's only somewhat related. I posted a question about the USRP
dynamic range a while ago (see link below) but didn't get a response.
Maybe you can comment on it.
The algorithm I used to calculate the figure on the Y axis was the sum
over an estimate of the power spectrum density.
Hi,
I think we are trying to do something different. We are trying to
investigate the possibility of increasing USRP dynamic range by modifying
some USRP FPGA stages.
By the way, what was the equation used to calculate the ADC output in dB in
you graph?
Firas
Jens Elsner wrote:
>
> I noticed
I noticed the discussion about the USRP dynamic range.
A while ago I made some measurements with a noise generator to calibrate
the USRP with a DBSRX daughterboard.
The resulting graph is attached.
Settings: room temperature, USRP, DBSRX, 2 MHz measurement bandwidth at
940 MHz center frequency,
