Eric Blossom wrote:
On Sat, Jun 18, 2005 at 01:26:27AM -0400, Krzysztof Kamieniecki wrote:
I confused as to how the USRP FPGA scales the ADC signal. It appears
that on the setup we are using, which has some customized DC Rx
daughter boards, when we put in a 2V p-p square wave with a DDC cent
On Sat, Jun 18, 2005 at 01:26:27AM -0400, Krzysztof Kamieniecki wrote:
> I confused as to how the USRP FPGA scales the ADC signal. It appears
> that on the setup we are using, which has some customized DC Rx
> daughter boards, when we put in a 2V p-p square wave with a DDC center
> frequency of
I confused as to how the USRP FPGA scales the ADC signal. It appears that on the setup we are using,
which has some customized DC Rx daughter boards, when we put in a 2V p-p square wave with a DDC
center frequency of zero and a decimation rate of 64 we are getting data that is p-p ~16000 counts,
