> "Matt" == Matt Ettus <[EMAIL PROTECTED]> writes:
>> 17) How much USRP2 FPGA resources does the currently FPGA firmware
>> needs?
>>
Matt> 37 out of 40 block RAMs, 16 or 18 of the 40 multipliers, and about
Matt> 35 to 40% of the logic area.
The XC3SD1800 would probably
Firas A. wrote:
But this is not clear in TX path because:
If Max IF Ethernate rate = 100 Mbyte/sec => Max TX IF bandwidth = 25 MHz
and if min interpolation = 4 (as you said in your previous email)
=> DAC will get 100 MSPS
But USRP2 DAC is clocked at 400 MHz, so where is the other missing
i
Hi Matt,
Thank you for the answers. I will try to add them to USRP2 FAQ Wiki.
One thing is not clear which is the TX path interpolation.
In RX path:
if ADC sampling = 100MHz,
and if Min decimation = 4
=> max IF bandwidth = 25MHz
=> Max IF Ethernet rate = 4 bytes per sample * 25 MSPS = 100 Mbyt
13) With Basic TX board, USRP1 can generate maximum of 44 MHz frequency,
What USRP2 is capable of ?
44 MHz is the highest frequency in the first nyquist zone on the USRP1.
Much higher frequencies can be used in the higher zones.
The USRP2 takes 100 MS/s rates and interpolates up to 400
Firas A. wrote:
Hi Matt,
I have some questions (prepared from a while before you have been submitted
USRP2 schematics so excuse me if some of them can be answered from your
schematics).
1) How USRP2 boots? and how the FPGA firmware is loaded?
The CPLD (a Xilinx XC9572) reads the 1st megab
Hi Matt,
I have some questions (prepared from a while before you have been submitted
USRP2 schematics so excuse me if some of them can be answered from your
schematics).
1) How USRP2 boots? and how the FPGA firmware is loaded?
2) What is USRP2 ADC chip? Is there an auxiliary ADC?
3) What is U
