Brian Padalino wrote:
On 3/29/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
"This way we don't
need a dual clock fifo that can skip, only a single clock one"
Yes, that's wrong, I wanted to say that we need only standard dual clock
fifo or single clock fifo that can skip packets but we don't n
Brian Padalino wrote:
On 3/29/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
"This way we don't
need a dual clock fifo that can skip, only a single clock one"
Yes, that's wrong, I wanted to say that we need only standard dual clock
fifo or single clock fifo that can skip packets but we don't n
On 3/29/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
"This way we don't
need a dual clock fifo that can skip, only a single clock one"
Yes, that's wrong, I wanted to say that we need only standard dual clock
fifo or single clock fifo that can skip packets but we don't need a dual
clock fifo t
Brian Padalino wrote:
On 3/29/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
My idea was that the process in the fpga that read usb_bus can store the
packet and the total length is reached, ignore the data coming because
we know its padding. That process is the first process in the wiki page
(
On 3/29/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
My idea was that the process in the fpga that read usb_bus can store the
packet and the total length is reached, ignore the data coming because
we know its padding. That process is the first process in the wiki page
(http://gnuradio.org/tra
Dan Halperin wrote:
George Nychis wrote:
Thibaud Hottelier wrote:
If any of that doesn't make sense, or people see it in a different way
- please feel free to comment and criticize.
It looks like your message did not arrive to mailing list! That
weird, it already happened to me once.
Off
George Nychis wrote:
> Thibaud Hottelier wrote:
>
>>> If any of that doesn't make sense, or people see it in a different way
>>> - please feel free to comment and criticize.
>>>
>>
>> It looks like your message did not arrive to mailing list! That
>> weird, it already happened to me once.
>
> Off t
Thibaud Hottelier wrote:
If any of that doesn't make sense, or people see it in a different way
- please feel free to comment and criticize.
It looks like your message did not arrive to mailing list! That weird,
it already happened to me once.
Off topic, but the message never arrived on
Brian Padalino wrote:
On 3/29/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
I CC'd the list, so Eric can participate to this discussion.
The more the merrier.
Yes but the only dual clock fifo is tx_usb_fifo, right? For this one we
can use the Altera dual clock fifo. The only fifos that ne
On Thu, Mar 29, 2007 at 10:56:09AM -0400, Thibaud Hottelier wrote:
> I CC'd the list, so Eric can participate to this discussion.
Thanks.
> Brian Padalino wrote:
> >On 3/28/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
> >>I noticed two things:
> >>
> >>The fifo does not need to be dual clock
Thibaud Hottelier wrote:
I CC'd the list, so Eric can participate to this discussion.
Can I participate too? :)
I think that for now we should remove the padding in the FPGA, because
it's easier. When everything will be working, then we can optimize it,
if that can bring some substantial b
On 3/29/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
I CC'd the list, so Eric can participate to this discussion.
The more the merrier.
Yes but the only dual clock fifo is tx_usb_fifo, right? For this one we
can use the Altera dual clock fifo. The only fifos that need the skip
command are
I CC'd the list, so Eric can participate to this discussion.
Brian Padalino wrote:
On 3/28/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
I noticed two things:
The fifo does not need to be dual clock because we only use it for the
tx_chan_fifo_X.
The FX2 directly toggles the writing side,
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