On 18/06/2014 01:25, Stephen Harrison wrote:
> There is a good treatment of errors in the CORDIC algorithm due to
> finite word length in this paper from IEEE transactions: The
> Quantization Effects of the CORDIC Algorithm (Yu Hen Hu, Senior Member,
> IEEE). I reproduced the results of section IV
I don't speak Verilog but I get the general gist of the code below.
Thanks. Cheers,
Daniele
On 18/06/2014 01:09, Stephen Harrison wrote:
> The Verilog source for the USRP N210 is available online. You can see
> this in ddc_chain.v:
>
> wire [31:0] phase_inc;
>reg [31:0] phase;
> ...
>
>
There is a good treatment of errors in the CORDIC algorithm due to finite
word length in this paper from IEEE transactions: The Quantization Effects
of the CORDIC Algorithm (Yu Hen Hu, Senior Member, IEEE). I reproduced the
results of section IV fairly easily a while ago. There are numerical errors
The Verilog source for the USRP N210 is available online. You can see this
in ddc_chain.v:
wire [31:0] phase_inc;
reg [31:0] phase;
...
setting_reg #(.my_addr(BASE+0)) sr_0
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(phase_inc),.changed());
...
Thanks for the answers.
I didn't think that the sine wave in the FPGA were generated with an
integer phase accumulator (I don't know much about how signal processing
is done in FPGAs). If this is the case, as I understand from Stephen
email, now I know where the frequency error comes from.
On th
Just some quick calculations in python:
exact phase increment for 10 MHz:
>>> (10e6/100e6)*2**32
429496729.6
Closest phase increment:
>>> np.round((10e6/100e6)*2**32)
429496730.0
Resulting frequency:
>>> (np.round(10e6/100e6*2**32)/2**32)*100e6
1000.009313226
We are out by 9.3mHz!
On T
Hi,
> To start I want to characterize the phase noise of the device, therefore
> I send to both the RX channel and to the frequency reference input the
> same 10 MHz signal. I configured the N210 for 200 kHz sampling and a
> carrier frequency of 10 MHz.
The LFTRX doesn't have a tuner so if you se
I did this exact experiment about a year ago. It's caused by the resolution
of the phase accumulator in the DDC.
On Tue, Jun 17, 2014 at 2:09 PM, Marcus D. Leech wrote:
> On 06/17/2014 04:56 PM, Daniele Nicolodi wrote:
>
>>
>> I'll try to see if this makes a difference. The minimum sampling rat
On 06/17/2014 04:56 PM, Daniele Nicolodi wrote:
I'll try to see if this makes a difference. The minimum sampling rate I
can program is ~193 kHz (it is a strange fraction that I cannot check
right now).
Minimum sample rate = 100e6/512
The USRP devices do strictly-integer decimation in the FPGA
Hello Marcus,
thank for your detailed response. Some comments and further questions:
On 17/06/2014 22:04, Marcus Müller wrote:
> The N210 has a fixed master clock rate of 100MHz, generated from the
> 10MHz reference by using PLL controlled clock multipliers.
> The ADC always samples at 100MHz com
Hello Daniele,
I've included the USRP users mailing list [1], since this is not related
to GNU Radio but to the USRP.
The N210 has a fixed master clock rate of 100MHz, generated from the
10MHz reference by using PLL controlled clock multipliers.
The ADC always samples at 100MHz complex, then pass
Hello,
I'm using an Ettus Research N210 with a LFRX daughter-board to do data
measure the phase of a signals referred to a 10 MHz clock.
To start I want to characterize the phase noise of the device, therefore
I send to both the RX channel and to the frequency reference input the
same 10 MHz sign
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