On Wed, Jun 23, 2010 at 11:27 AM, Yan Nie wrote:
> Is it possible to change the sampling rate of D/A converter to 64MHz? I saw
> the sampling rate of D/A converter is defined in usrp_basic.cc, which is
> fpga_master_clock_freq() * 2. Is it possible to make the master clock
> frequency not multiply
Dear all,
Is it possible to change the sampling rate of D/A converter to 64MHz? I saw the
sampling rate of D/A converter is defined in usrp_basic.cc, which is
fpga_master_clock_freq() * 2. Is it possible to make the master clock frequency
not multiply by 2? Can it be changed in python when the