Yes! that seems to be doing it.
After using u.set_dc_offset_cl_enable(0x0, 0xf) to disable the dc
correction the Low Freq roll-off seems to be gone and my IQ looks a
lot better.
That's really excelent, I presume I'll still need to compensate for
the dc in my flow graph now though...
Many thanks!
D
On 11/04/2010 07:47 PM, Eric Brombaugh wrote:
>
> You're probably seeing the high-pass behavior of the RX DC offset
> removal. There's a logical block inside the FPGA which integrates the
> ADC DC offset and subtracts it from the incoming signal.
>
> This function isn't needed on the TX side.
>
>
W
On 11/04/2010 04:24 PM, Drew Read wrote:
It seems that there is a very significant roll-off at lower
frequencies on the receive side which pretty much makes it unusable
for our baseband signals.
The aformentioned forum post suggests that it is not caused by the
LFRX board and so is likely to be
On 11/04/2010 07:24 PM, Drew Read wrote:
> Hi All,
>
> We're seeing pretty much the same thing on the USRP1 as this:
> http://www.ruby-forum.com/topic/206912#900641
>
> It seems that there is a very significant roll-off at lower
> frequencies on the receive side which pretty much makes it unusable
Hi All,
We're seeing pretty much the same thing on the USRP1 as this:
http://www.ruby-forum.com/topic/206912#900641
It seems that there is a very significant roll-off at lower
frequencies on the receive side which pretty much makes it unusable
for our baseband signals.
The aformentioned forum pos
