On Thu, Apr 26, 2007 at 01:56:10PM -0400, Brian Padalino wrote:
> When the FX2 detects the have_space pin on the FPGA, does it transfer
> 1 entire buffered USB packet to the FPGA, then re-check the have_space
> pin?
Yes.
> Would it be reasonable to assume a 1 clock delay between the last byte
> o
When the FX2 detects the have_space pin on the FPGA, does it transfer
1 entire buffered USB packet to the FPGA, then re-check the have_space
pin?
Would it be reasonable to assume a 1 clock delay between the last byte
of one 512-byte packet being written to the FPGA and the first byte of
a second
