Peter Monta wrote:
Could FPGA jitter be contributing? It can be hundreds of picoseconds,
but whether there would be low-frequency content in the jitter spectrum
I don't know.
FPGA jitter might be contributing, but there shouldn't be much at low
frequency. You could try measuring this by s
I tried Greg Heckler's suggestion of minimizing the reference divisor---when
running rx_cfile.py, giving a frequency of 1.57542G results in a reference
divisor of 8, whereas a frequency of 1.574G decreases this to 2. (I also
probed at the chip and saw the same inexplicable factor of two disparity
