Hi all Based on the instructions in the following link: http://files.ettus.com/manual/md_usrp3_build_instructions.html I downloaded fpga source code for E310 and attempted to build FPGA image in cygwin environment
The fpga source code is downloaded from https://github.com/EttusResearch/fpga/tree/master/usrp3 After tens of minutes, the building procedure was ended with some errors which are listed in the following lines. But I am not sure what these error really means and how to avoid them. Any suggestions are really appreciate. Cheers! **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. source {D:\usrp3\tools\scripts\viv_generate_ip.tcl} # set xci_file $::env(XCI_FILE) ; # set part_name $::env(PART_NAME) ; # set gen_example_proj $::env(GEN_EXAMPLE) ; # set synth_ip $::env(SYNTH_IP) ; # set ip_name [file rootname [file tail $xci_file]] ; # file delete -force "$xci_file.out" # create_project -part $part_name -in_memory -ip # set_property target_simulator XSim [current_project] # add_files -norecurse -force $xci_file INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2015.4/data/ip'. Loading device for application Rf_Device from file '7z020.nph' in environment D:/Xilinx/Vivado/2015.4/ids_lite/ISE. child killed: floating-point exception [31mERROR: [IP_Flow 19-3475] Tcl error in ::ipgui_mig_7series_0::updateAllModelParams procedure for IP 'mig_7series_0'. Loading device for application Rf_Device from file '7z020.nph' in environment (B[mD:/Xilinx/Vivado/2015.4/ids_lite/ISE. child killed: floating-point exception add_files: Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 272.992 ; gain = 67.289 [31mERROR: [Common 17-39] 'add_files' failed due to earlier errors. (B[m while executing "add_files -norecurse -force $xci_file" (file "D:\usrp3\tools\scripts\viv_generate_ip.tcl" line 22) INFO: [Common 17-206] Exiting Vivado at Wed Nov 23 01:59:03 2016... BUILDER: Releasing IP location: /cygdrive/d/usrp3/top/e300/build-ip/xc7z020clg484-1/mig_7series_0 make[1]: *** [/cygdrive/d/usrp3/top/e300/ip/mig_7series_0/Makefile.inc:32: /cygdrive/d/usrp3/top/e300/build-ip/xc7z020clg484-1/mig_7series_0/mig_7series_0.xci] Error 1 make[1]: Leaving directory '/cygdrive/d/usrp3/top/e300' make: *** [Makefile:44: E310] Error 2 Peter
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