If we had an fpga image that allowed us to store samples on the USRP2
that would be very benefitial, at least for me. Then one could test
algorithms with 100MHz sample-rate. Yes, it would not be possible to
use the channel continously. Receiving 1ms of samples would take 4ms
to upload. Howeve
Eric A. Cottrell wrote:
Philip Balister wrote:
On Fri, Aug 1, 2008 at 6:31 PM, Eric Brombaugh <[EMAIL PROTECTED]>
wrote:
On Aug 1, 2008, at 1:58 PM, Philip Balister wrote:
I've been talking to a friend (he knows FPGA stuff much better than
me) about using the expansion port to communic
