). But yet there is about 1MHz frequency offset between TX and RX
and that is the reason I thought their are not locked to the ref clock.
Why would I still observe about 1MHz frequency offset then?
On 2/23/2011 2:32 PM, Ed Criscuolo wrote:
On 2/23/11 4:07 PM, Malihe Ahmadi wrote:
Hi,
I have
contain API
information if you need more specifics.
--n
On Thu, 2011-01-06 at 09:03 -0700, Malihe Ahmadi wrote:
Hi Nick,
can you please explain more about the requirement of the external clock?
and what do you mean by enabling reference clock? I need more
information..., any doc I can read?
Thanks
Hi,
I am testing a transceiver link in ISM band using two USRP2+RFX2400, one
configured as TX and the other one as RX. I would like to test my own
FPGA program, so for now I have your FPGA codes in which I only changed
the signal driving the DAC in TX to be an square wave (+8191 or -8192)
wit
HI,
I would like to configure two USRP2+RFX2400 boards one as the TX only
and the other one as RX only, so on the TX board I set:
io_tx_05=1 => the enable(pin 8)of the transmitter mixer (U101) is
always high, so the mixer is always active
io_tx_06=0 => the TX/RX (U202) works always as TX
a
Hi Nick,
I have a USRP2 + RFX2400 which I'd like to use as a transceiver. here
are my questions:
1- Assuming I get two antennas, one connected to TX/RX port and the
second one connected to RX2 port, Can I get the first antenna to act as
the TX (driven only by DAC) and the second one act as RX
root.
If you only specify an FPGA image when you run the program, the firmware
image will not be overwritten.
Nick
On Wed, 2010-09-15 at 12:27 -0600, Malihe Ahmadi wrote:
I have changed the FPGA code and I have built the bit file for it. I
would like to keep the same firmware but just change
I have changed the FPGA code and I have built the bit file for it. I
would like to keep the same firmware but just change the FPGA code. What
should I do now?
Thanks,
Malihe
Nick Foster wrote:
Malihe,
Your understanding is basically correct. I misunderstood your request -- I
didn't realize
Hi,
what is the speed grade of XC3S2000 FPGA on USRP2 board?
Thanks,
Malihe
___
Discuss-gnuradio mailing list
Discuss-gnuradio@gnu.org
http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
Hi Nick,
I think I should explain my project better. We are developing a physical
layer protocol for an asynchronous packet based transceiver all in
Verilog. The design has been simulated so far using ModelSim. The target
of the project is the VLSI fabrication of this design. Thus all the
sig
sted in removing Ethernet and using debug bus to pass stream of
data to the FPGA?
Thanks,
Malihe
Marcus D. Leech wrote:
On 09/02/2010 02:48 PM, Malihe Ahmadi wrote:
I need 5 mega bit per sec of bandwidth and if I understand correct
the rate of CMII_TX_CLK is 100 mega bit per second which is higher
t
Hi Nick,
Actually we are using the USRP2 not for a SDR application, but we are
using it to test our physical layer asynchronous backet based
communication. For that I have to change the FPGA code and remove the
interpolation/decimation and replace it with a spreading scheme. for
that I need t
Hi Nick,
Actually we are using the USRP2 not for a SDR application, but we are
using it to test our physical layer asynchronous backet based
communication. For that I have to change the FPGA code and remove the
interpolation/decimation and replace it with a spreading scheme. for
that I need t
0 at 07:07:26PM -0600, Malihe Ahmadi wrote:
Hi,
I am using USRP2+RFX2400 board and trying to adapt our packetized
communication on the board. As I understand the Ethernet does its
own packetization on information data and we don't like that.
therefore we are looking into avoid passing our inf
Hi,
I am using USRP2+RFX2400 board and trying to adapt our packetized
communication on the board. As I understand the Ethernet does its own
packetization on information data and we don't like that. therefore we
are looking into avoid passing our information data to the board through
Ethernet.
14 matches
Mail list logo