I'm trying to make some modifications to the FPGA of the USRP2 which
involves using more multipliers and I came across this error during
the Mapping phase of the compile:
ERROR:Place:665 - The design has 31 block-RAM components of which 13 block-RAM
components require the adjacent multiplier si
e
DDCs running from one NCO(needed to clear up space on the FPGA). The
channels are alligned after you deinterleave them, however using the
standard build I am not sure if you will have a phase difference
between your NCOs.
-Kyle Pearson
>
> Thanks in advance, and sorry for the multiple qu
> Matt made some changes in the USRP2 FPGA and firmware code in
> changeset 10762 that we believe fixes this problem.
>
> Can you please download and try the lastest FPGA image and firmware
> from http://gnuradio.org/releases/usrp2-bin/trunk and let us know if
> this fixes it for you.
>
> FYI, at h
> However, if you buy some more hardware, you can drive both USRP2 and
> USRP1 from the same clock. The USRP2 takes a 10 MHz standard, but the
> USRP2 needs a 64 MHz clock.
You can actually use a common reference between the USRP1 and USRP2 by
modifying some of the USRP2 firmware code so that it c
just updated to rev. 10479 off svn. Has anyone else had these issues
or is everyone else fine on Linux and/or ISE 10.1?
Thanks,
Kyle Pearson
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pins labeled Test CLK are? Can they
be used to see the clock after locking it to the external reference?
Thanks,
Kyle
On Wed, Oct 22, 2008 at 5:44 PM, Matt Ettus <[EMAIL PROTECTED]> wrote:
> Kyle Pearson wrote:
>>
>> I'm aware that the internal clock can be locked to an
at 04:12:07PM -0400, Kyle Pearson wrote:
>> I'm wondering if it is possible to connect the USRP2 to an external
>> 100MHz clock like the USRP was able to be modified so it could connect
>> to an external 64MHz clock. I don't see any place to solder on a SMA
>> connec
I'm wondering if it is possible to connect the USRP2 to an external
100MHz clock like the USRP was able to be modified so it could connect
to an external 64MHz clock. I don't see any place to solder on a SMA
connector but there are a set of pins labeled Test CLK. Could that be
used for inputting an
Newell-
I don't remember exactly, but when I did this about 60% of the FPGA
resources were used.
-Kyle
On Thu, Oct 16, 2008 at 12:45 AM, Newell Jensen <[EMAIL PROTECTED]> wrote:
> Does anyone know just how much resources will be freed up by doing the
> following (this is one of the FPGA/Verilog q
On Wed, Oct 8, 2008 at 12:20 PM, Kyle Pearson
<[EMAIL PROTECTED]> wrote:
> On Tue, Oct 7, 2008 at 6:36 PM, Karthik Vijayraghavan
> <[EMAIL PROTECTED]> wrote:
>> On Tue, Oct 7, 2008 at 3:01 PM, Kyle Pearson
>> <[EMAIL PROTECTED]> wrote:
>>> I down
On Tue, Oct 7, 2008 at 6:36 PM, Karthik Vijayraghavan
<[EMAIL PROTECTED]> wrote:
> On Tue, Oct 7, 2008 at 3:01 PM, Kyle Pearson
> <[EMAIL PROTECTED]> wrote:
>> I downloaded rev. 9728 from the svn today and after installing it when
>> I tried to run find_u
I downloaded rev. 9728 from the svn today and after installing it when
I tried to run find_usrps I got the following error:
find_usrps: error while loading shared libraries: libusrp2.so.0:
cannot open shared object file: No such file or directory
I am running Ubuntu 8.04 (Hardy) and I followed th
On Wed, Oct 1, 2008 at 3:43 PM, Eric Blossom <[EMAIL PROTECTED]> wrote:
> On Wed, Oct 01, 2008 at 02:53:40PM -0400, Kyle Pearson wrote:
>> I'm looking to model the rx_chain of the USRP using MATLAB's fixed
>> point toolbox and I'm wondering if anyone has t
I'm looking to model the rx_chain of the USRP using MATLAB's fixed
point toolbox and I'm wondering if anyone has tried this yet in MATLAB
or Octave.
Thanks,
Kyle
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You can connect the 1PPS to the digital io pins on the basic or lf
daughtercards. From there you can use the read_io() method in python
to read the value on the pins. Just make sure that your 1PPS is
between about 1.5 and 3.3V; under 1.5V it may not be detected, over
3.3V you could fry a pin.
-Kyl
Could someone please tell me the DC Offset value stored in the EEPROM
of the LFRX Daughterboard?
Thanks,
Kyle
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