Can we implement some block in FPGA to reduce the CPU consumption?
Have any work like this done already ?
Thanks
Jing
On Mon, Dec 15, 2008 at 12:36 PM, Johnathan Corgan
wrote:
> On Fri, Dec 12, 2008 at 4:48 PM, Marcus D. Leech wrote:
>
>> I think what's happening is that the I/O thread is goi
I figured out a method to set interpolation correctly. Before the
interpolation is set, we have to flush out all the data from the
transmit path. Now I do it by sleep for a while before I set the
interpolation.
The best solution is there is a indicator to show whether the
transmitting path is empt
