Dear all,I am using N210, I wan to bring "AA17" pin of FPGA to up 3.3v, and
how can use UHD to do that?
Josh replied me that make a new settings register in u2plus_core.v and use
set_user_register() to control it.but I read the u2plus_core.v code, and
try to add the setting_reg to
Michael,
1) For 8 bit you change the wire format parameter of the UHD Source and
Sink from "automatic" to "sc8". This is one of the options you get when
double clicking the Source/Sink in GRC. Changing the output type of the
block in GRC has no effect on the wire format. No modification to
ha
Adaptive filtering, whether FIR or IIR, will change the taps dynamically.
I love the design tool idea.
Bob
On Wednesday, July 25, 2012, sreeraj r wrote:
>
> >I didnt mean to imply that there was some kind of formal discussion tool
> >like a forum thread. I was just referring to these emails:
>
>I didnt mean to imply that there was some kind of formal discussion tool
>like a forum thread. I was just referring to these emails:
>
>https://lists.gnu.org/archive/html/discuss-gnuradio/2012-05/msg00142.html
>
>https://lists.gnu.org/archive/html/discuss-gnuradio/2012-05/msg00146.html
>I think
Thank you for reading this.
I received my HF up converter (the companion for the Funcube dongle) in
the mail today but disappointingly I cannot hear anything but noise. The
spectrogram shows a lot of activity which I suspect is noise generated
by the laptop.
Has anyone had success with this
I have a few queries regarding some of the options for improving the
performance of the XCVR2450 + N210.
1) The N210 can offer 50MSPS with 8 bit I&Q samples or 25MSPS with 16bit
1&Q.
If using 16 bit I &Q samples, I'd just leave the UHD input block with
"Complex int 16".
How do I implement 8 bit I&
