Okay, I can't seem to get past this one which is blocking my progress.
I understand that usrp-server-cs and usrp-tx ... etc are all defined in the
usrp_server.mbh file which gets translated to usrp_server_mbh.cc which is built.
According to the inband Makefile.am, it should be included in the
Brian Padalino wrote:
On 4/22/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
Brian Padalino wrote:
I have just refactored the code so that the fifos are out of the
readers. I also added samples format handling (only 16 bits interleaved
complex so far). I am looking forward to testing this;
On 4/22/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
Brian Padalino wrote:
I have just refactored the code so that the fifos are out of the
readers. I also added samples format handling (only 16 bits interleaved
complex so far). I am looking forward to testing this; George told me he
will be
Brian Padalino wrote:
I have just refactored the code so that the fifos are out of the
readers. I also added samples format handling (only 16 bits interleaved
complex so far). I am looking forward to testing this; George told me he
will be able to send usb packets on Tuesday.
Perfect.
Yes
Hi,
I am interested in building a radio receiver, using GNUR.
Could someone comment whether a motorola surfman cable modem maybe used, for
the purpose?
GB
_
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On 4/22/07, Eng. Firas <[EMAIL PROTECTED]> wrote:
Dear Matt,
Dear All,
Is the DDC decimate by 2 half band filter built inside the FPGA ? If it is
so, then how much the free available FPGA resources left after building all
the present USPR circuits in it? I mean, is there a free space to modify
On 4/22/07, Eng. Firas <[EMAIL PROTECTED]> wrote:
Thank you Brian, Matt.
If the CIC starts linearly from 4 to 128, and followed by decimate by 2 Half
Band Filter (HBF) Then [CIC+HBF] should give us the following range
[8,10,12,14,...,256], and not the range [2,4,6,8,..,256] , is
thi
Brian Padalino wrote:
>
> On 4/22/07, Eng. Firas <[EMAIL PROTECTED]> wrote:
>>
>> Dear Matt,
>> Dear All,
>>
>>
>> Is the DDC decimate by 2 half band filter built inside the FPGA ? If it
>> is
>> so, then how much the free available FPGA resources left after building
>> all
>> the present USPR
