--- John Clark <[EMAIL PROTECTED]> wrote:
> I've been asked about getting the code we are using running on a
> Windows
Not quite what you asked but...
Try VMware. They have made VMware Player free. Have your
users install that then you send them a .ZIP file with the Linux
VM image on it. Yo
On Thu, Mar 29, 2007 at 06:27:24PM -0700, Dan Halperin wrote:
> Eric Blossom wrote:
> > On Thu, Mar 29, 2007 at 05:16:45PM -0700, Dan Halperin wrote:
> >
> >> Since this block initially starts with 0 inputs and is not filled with
> >> other data following the run of the program, the last <10 sam
Eric Blossom wrote:
> On Thu, Mar 29, 2007 at 05:16:45PM -0700, Dan Halperin wrote:
>
>> Greg Troxel wrote:
>>
>>> I wonder if there is data somewhere in the flowgraph that's less than
>>> the amount needed for the next block to run. Perhaps there should
>>> be some sort of drain operatio
On Thu, Mar 29, 2007 at 05:16:45PM -0700, Dan Halperin wrote:
> Greg Troxel wrote:
> > I wonder if there is data somewhere in the flowgraph that's less than
> > the amount needed for the next block to run. Perhaps there should
> > be some sort of drain operation, or query for this (that adds over
Greg Troxel wrote:
> I wonder if there is data somewhere in the flowgraph that's less than
> the amount needed for the next block to run. Perhaps there should
> be some sort of drain operation, or query for this (that adds over
> components), so one can find out what's going on.
>
This appear
Brian Padalino wrote:
On 3/29/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
"This way we don't
need a dual clock fifo that can skip, only a single clock one"
Yes, that's wrong, I wanted to say that we need only standard dual clock
fifo or single clock fifo that can skip packets but we don't n
Brian Padalino wrote:
On 3/29/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
"This way we don't
need a dual clock fifo that can skip, only a single clock one"
Yes, that's wrong, I wanted to say that we need only standard dual clock
fifo or single clock fifo that can skip packets but we don't n
On 3/29/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
"This way we don't
need a dual clock fifo that can skip, only a single clock one"
Yes, that's wrong, I wanted to say that we need only standard dual clock
fifo or single clock fifo that can skip packets but we don't need a dual
clock fifo t
Brian Padalino wrote:
On 3/29/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
My idea was that the process in the fpga that read usb_bus can store the
packet and the total length is reached, ignore the data coming because
we know its padding. That process is the first process in the wiki page
(
On 3/29/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
My idea was that the process in the fpga that read usb_bus can store the
packet and the total length is reached, ignore the data coming because
we know its padding. That process is the first process in the wiki page
(http://gnuradio.org/tra
On Thu, Mar 29, 2007 at 01:10:58PM -0700, Candy Yiu wrote:
> Hi,
>
> I am trying to do beamforming using 2 RFX 2400 boards. I am facing an
> issue with setting the mux value (to set ADC connection to DDC and/or
> DUC connection to DAC) on transmitter and receiver side. On the
> transmitter side
I just got Vista myself, and I noticed a feature you
can enable called Subsystem for Unix Applications. I
haven't had time to try it yet, but I believe that
will let you install GNURadio. If I find out anything
else, I'll let you know.
John Bratteli
Hi,
I am trying to do beamforming using 2 RFX 2400 boards. I am facing an
issue with setting the mux value (to set ADC connection to DDC and/or
DUC connection to DAC) on transmitter and receiver side. On the
transmitter side I am using the value 0xba98 and I think this works. On
the receiver
Dan Halperin wrote:
George Nychis wrote:
Thibaud Hottelier wrote:
If any of that doesn't make sense, or people see it in a different way
- please feel free to comment and criticize.
It looks like your message did not arrive to mailing list! That
weird, it already happened to me once.
Off
I've been asked about getting the code we are using running on a Windows
XP or Vista based box.
Is there a 'easy' to understand installable package, or do I have to
setup a cygwin environment
(or having set cygwin up, is there a packaged tar image...), and then
compile from sourced
to get thi
George Nychis wrote:
> Thibaud Hottelier wrote:
>
>>> If any of that doesn't make sense, or people see it in a different way
>>> - please feel free to comment and criticize.
>>>
>>
>> It looks like your message did not arrive to mailing list! That
>> weird, it already happened to me once.
>
> Off t
Thibaud Hottelier wrote:
If any of that doesn't make sense, or people see it in a different way
- please feel free to comment and criticize.
It looks like your message did not arrive to mailing list! That weird,
it already happened to me once.
Off topic, but the message never arrived on
Brian Padalino wrote:
On 3/29/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
I CC'd the list, so Eric can participate to this discussion.
The more the merrier.
Yes but the only dual clock fifo is tx_usb_fifo, right? For this one we
can use the Altera dual clock fifo. The only fifos that ne
Dan Halperin wrote:
>
> DiX wrote:
>> So I should update the SWIG to 1.3.31, right? Then how to call
>> bin_statistics_f that is not in the Gnuradio 3.0 please? Thanks in
>> advance.
>>
>> DiX
>>
> You'll want to uninstall the code you're using from the tarballs and
> install from the tr
On Thu, Mar 29, 2007 at 03:46:12PM +0100, eenrti wrote:
> Hello,
> I have used a sinusoidal signal generator to test my USRP output stream
> using a single or even the teo inputs to the RX daughterboard.
> I suppose there are 4 channels at the end when I use both RX
> daughterboard inputs, for I
DiX wrote:
> So I should update the SWIG to 1.3.31, right? Then how to call
> bin_statistics_f that is not in the Gnuradio 3.0 please? Thanks in advance.
>
> DiX
>
You'll want to uninstall the code you're using from the tarballs and
install from the trunk. To install from the trunk, see:
ht
Eric Blossom wrote:
>
> On Thu, Mar 29, 2007 at 08:23:23AM -0700, DiX wrote:
>
>>
>
> (1) bin_statistics_f is in the trunk, not in any of the tarballs.
> (2) For the trunk you'll need to use SWIG 1.3.31
>
> Eric
>
>
>
So I should update the SWIG to 1.3.31, right? Then how to call
bin_
On Thu, Mar 29, 2007 at 08:23:23AM -0700, DiX wrote:
>
> Hi guys,
>
> I am trying to scan the channel6 of 802.11b with
> "usrp_spectrum_sense.py". However it fails with the following error:
>
> Using RX d'board A: TV Rx
> Traceback (most recent call last):
>File "./usrp_spectrum_sen
Dan Halperin wrote:
> This is the final state of the flow graph:
>
> regular 2:1
> max_items_avail = 9
> noutput_items = 8191
> BLKD_IN
> were_done
I realized that the other two flow graph elements with max_items_avail >
0 have the same max_items_avail at initialization; this makes sense
On Thu, Mar 29, 2007 at 10:56:09AM -0400, Thibaud Hottelier wrote:
> I CC'd the list, so Eric can participate to this discussion.
Thanks.
> Brian Padalino wrote:
> >On 3/28/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
> >>I noticed two things:
> >>
> >>The fifo does not need to be dual clock
DiX wrote:
Hi guys, I am trying to scan the channel6 of 802.11b with
"usrp_spectrum_sense.py". However it fails with the following error:
Using RX d'board A: TV Rx Traceback
Your problem is that the TVRX only goes up to 860 MHz, so it can't tune
to 802.11 channels at 2.4 GHz. If you have b
(Eric, sorry I keep failing to reply all)
Eric Blossom wrote:
> On Thu, Mar 29, 2007 at 08:01:38AM -0700, Eric Blossom wrote:
>
>> On Thu, Mar 29, 2007 at 08:04:22AM -0400, Greg Troxel wrote:
>>
>>> I wonder if there is data somewhere in the flowgraph that's less than
>>> the amount needed
Rigas,
It is not necessary to cc: Eric and me when sending a message to the GNU
Radio mailing list, since we are on the list. Sending 2 copies of your
message in 15 minutes is also not necessary.
I have used a sinusoidal signal generator to test my USRP output
stream using a single or even
Hi guys,
I am trying to scan the channel6 of 802.11b with
"usrp_spectrum_sense.py". However it fails with the following error:
Using RX d'board A: TV Rx
Traceback (most recent call last):
File "./usrp_spectrum_sense.py", line 236, in ?
fg = my_graph()
File "./usrp_spectrum_sense.py
Hi guys,
I am trying to scan the channel6 of 802.11b with
"usrp_spectrum_sense.py". However it fails with the following error:
Using RX d'board A: TV Rx
Traceback (most recent call last):
File "./usrp_spectrum_sense.py", line 236, in ?
fg = my_graph()
File "./usrp_spectrum_sens
Hi guys,
I am trying to scan the channel6 of 802.11b with
"usrp_spectrum_sense.py". However it fails with the following error:
Using RX d'board A: TV Rx
Traceback (most recent call last):
File "./usrp_spectrum_sense.py", line 236, in ?
fg = my_graph()
File "./usrp_spectrum_se
Thibaud Hottelier wrote:
I CC'd the list, so Eric can participate to this discussion.
Can I participate too? :)
I think that for now we should remove the padding in the FPGA, because
it's easier. When everything will be working, then we can optimize it,
if that can bring some substantial b
Hello everyone. I am working on Amplitude demodulation. I am using the
attached python code. I have some doubts as to why particular frequencies
are chosen. Firstly, in the code
*channel_coeffs = gr.firdes.low_pass (1.0, if_rate, 8000, 1000,
gr.firdes.WIN_HANN)*
Why a cut off frequency of 80
On 3/29/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
I CC'd the list, so Eric can participate to this discussion.
The more the merrier.
Yes but the only dual clock fifo is tx_usb_fifo, right? For this one we
can use the Altera dual clock fifo. The only fifos that need the skip
command are
On Thu, Mar 29, 2007 at 08:01:38AM -0700, Eric Blossom wrote:
> On Thu, Mar 29, 2007 at 08:04:22AM -0400, Greg Troxel wrote:
> >
> > I wonder if there is data somewhere in the flowgraph that's less than
> > the amount needed for the next block to run. Perhaps there should
> > be some sort of dra
I CC'd the list, so Eric can participate to this discussion.
Brian Padalino wrote:
On 3/28/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
I noticed two things:
The fifo does not need to be dual clock because we only use it for the
tx_chan_fifo_X.
The FX2 directly toggles the writing side,
On Thu, Mar 29, 2007 at 08:04:22AM -0400, Greg Troxel wrote:
> Eric Blossom <[EMAIL PROTECTED]> writes:
>
> > On Wed, Mar 28, 2007 at 09:39:14PM -0700, Dan Halperin wrote:
> >> Same loopback code I emailed about earlier; this time I attached the
> >> complete file (modulo some cleanup).
> >>
> >
Hello,
I have used a sinusoidal signal generator to test my USRP output stream
using a single or even the teo inputs to the RX daughterboard.
I suppose there are 4 channels at the end when I use both RX
daughterboard inputs, for I and Q so I tried to separate my output data
by using a 4 sample
Hello,
I have used a sinusoidal signal generator to test my USRP output stream
using a single or even the teo inputs to the RX daughterboard.
I suppose there are 4 channels at the end when I use both RX
daughterboard inputs, for I and Q so I tried to separate my output data
by using a 4 sample
Eric Blossom <[EMAIL PROTECTED]> writes:
> On Wed, Mar 28, 2007 at 09:39:14PM -0700, Dan Halperin wrote:
>> Same loopback code I emailed about earlier; this time I attached the
>> complete file (modulo some cleanup).
>>
>> Here's my input file (in stupid x86 short ordering..):
>>
>>$ hexdum
Hello,
Can anyone please tell me how do I interface the USRP with Matlab and Code
Composer Studio?
I am doing some work on the fpga, so more or less, the work will be with the
CCS.
Any help in this regard would be appreciated.
Thanks a lot.
Regards,
Kuntal
--
View this message in context:
ht
Eric Blossom wrote:
On Wed, Mar 28, 2007 at 09:39:14PM -0700, Dan Halperin wrote:
Same loopback code I emailed about earlier; this time I attached the
complete file (modulo some cleanup).
Here's my input file (in stupid x86 short ordering..):
$ hexdump input.txt
000 bbaa ddcc ffe
On Wed, Mar 28, 2007 at 09:39:14PM -0700, Dan Halperin wrote:
> Same loopback code I emailed about earlier; this time I attached the
> complete file (modulo some cleanup).
>
> Here's my input file (in stupid x86 short ordering..):
>
>$ hexdump input.txt
>000 bbaa ddcc ffee 1100 3322
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