On Mar 22, 2007, at 5:11 PM, Jonathan Shan wrote:
On Thu, 22 Mar 2007, Johnathan Corgan wrote:
Jonathan Shan wrote:
When I send this to file_sink, I see correctly 16 samples from
peak to
peak. However, when I transmit this using 'usrp sink' and receive
at the
other end, I see about 32
Hello,
When running "make check" as outlined in the gr-howto-write-a-block
tutorial, I am receiving a segmentation fault. I am running Ubuntu 6.10
(Edgy Eft) with linux kernel release 2.6.17-11-386 and GNU Radio 3.0. GNU
Radio is otherwise functional, as I successfully run usrp_fft.py and
benchm
Hi,
I am little skeptical whether transceiver function of RFX2400 works well or
not? If anyone has been successfull in implementing ARQ on wireless packet
radio, please help me out and enlight me with the implementation. I need to
give a demo on JPEG/MPG transmission and reception so that we can
A quick update while I am understanding your previous message.
It looks like each Rx chain takes up 3 blocks, but the Tx chains does
not use any memory block. (Actually Tx0 uses one block but not Tx1).
The Rx and Tx buffers use 16 blocks each.
Thibaud
Brian Padalino wrote:
On 3/22/07, Thib
Jonathan Shan wrote:
>> What do you have the transmitter interpolation and receiver decimation
>> set to?
>
> interp_rate = 64, decim_rate = 16.
>
> I saw the formulas
> usb_sample_rate1 = 64e6 / decim_rate
> usb_sample_rate2 = 128e6 / interp_rate
>
> Using current values, usb_rate1 = 2 * usb_r
On Thu, 22 Mar 2007, Johnathan Corgan wrote:
Jonathan Shan wrote:
When I send this to file_sink, I see correctly 16 samples from peak to
peak. However, when I transmit this using 'usrp sink' and receive at the
other end, I see about 32 samples from peak to peak.. double what I
expected. What
On 3/22/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
So the fpga would only use fifo and push the data to next one. It does
not work if shared RAM is used to avoid copy between buffers; or I am
completely wrong and I fail to understand your point.
You are correct on that one unless you setu
Brian Padalino wrote:
On 3/22/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
I can copy the sample to a fifo, but I still have 3 processes that want
to use the RAM a the same time: One to progressively store the packets
coming from the usb bus, one to copy the samples into the corresponding
ch
On 3/22/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
I can copy the sample to a fifo, but I still have 3 processes that want
to use the RAM a the same time: One to progressively store the packets
coming from the usb bus, one to copy the samples into the corresponding
channel fifo and one to c
"Rohit Gupta" <[EMAIL PROTECTED]> writes:
> What if I use "two" GNURAdio boards at the same time, one for TX and another
> for RX. However, they are now placed very close to each other(say <10cm). Do
> you think this will be a good idea to achieve isolation between TX and RX
> chains??
That will
Brian Padalino wrote:
On 3/22/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
Yes, I forgot that the packet are ordered by timestamps, which solved
the fragmentation issues. However I cannot find an Altera RAM
megafunction that provides more that two independent ports. This is not
enough and wi
Hi Greg,
Thanks.
What if I use "two" GNURAdio boards at the same time, one for TX and another
for RX. However, they are now placed very close to each other(say <10cm). Do
you think this will be a good idea to achieve isolation between TX and RX
chains??
Rohit
On 3/22/07, Greg Troxel <[EMAIL P
Jonathan Shan wrote:
> When I send this to file_sink, I see correctly 16 samples from peak to
> peak. However, when I transmit this using 'usrp sink' and receive at the
> other end, I see about 32 samples from peak to peak.. double what I
> expected. What is happening?
What do you have the transm
Hello,
At the transmitting end, I have defined a sine wave using:
gr.sig_source_c(sampling_freq, gr.GR_SIN_WAVE, baseband_freq, .. )
Such that: sampling_freq = 16 * baseband_freq
When I send this to file_sink, I see correctly 16 samples from peak to
peak. However, when I transmit this using
On Thu, Mar 22, 2007 at 10:17:05AM +0100, Davide Anastasia wrote:
> Il giorno mer, 21/03/2007 alle 10.57 -0700, Eric Blossom ha scritto:
> > Does your PYTHONPATH point to the location
> > that you're installing to?
>
> My PYTHONPATH is empty. What is contains usually?
> --
> Davide Anastasia
You
On 3/22/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
Yes, I forgot that the packet are ordered by timestamps, which solved
the fragmentation issues. However I cannot find an Altera RAM
megafunction that provides more that two independent ports. This is not
enough and will prevent the FPGA fro
Brian Padalino wrote:
On 3/21/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
So, if I have correctly understood, I would use dual_clock ram component
(altsyncram for instance) and only pass the packet address (and maybe
its length) to the next block. If the whole packet (including padding)
is
"Rohit Gupta" <[EMAIL PROTECTED]> writes:
> I have question regarding the full duplex operation of RFX2400 board.
> Looking at the circuit diagram of the board, I understand that each RFX2400
> board has seperate receive AND transmit chain. Hence, if I connect one
> antenna to "RX" port and anoth
Hello
Can i know the exact functionality of usrp_std.v . which is inside
radio\usrp\fpga\toplevel\usrp_std at GNU radio/wiki.
i tried to understand this program but getting difficulty in understanding this.
Also it includes 2 more Verilog files
fpag_regs_standard.v
and
fpag_regs_common.
Il giorno mar, 20/03/2007 alle 10.09 +0100, Davide Anastasia ha scritto:
> > Maybe we should make gr_complex_short be a typedef for
> > complex
> > and output those.
>
> Yep, in this way std::complex make conversion between float and short
> transparently. Ok, I'll work in this direction. Actua
Hi,
I have question regarding the full duplex operation of RFX2400 board.
Looking at the circuit diagram of the board, I understand that each RFX2400
board has seperate receive AND transmit chain. Hence, if I connect one
antenna to "RX" port and another different antenna to "TX/RX" port and use
t
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