Hi everybody,
What we can configure to the FPGA and How much the maximum gate in the
FPGA? What HDL file that needed to use the FPGA in the USRP? Can I use
VHDL code besides Verilog?
Thanks.
Mahendra
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Himy name is Ivan Ferraro. I'm implementing USRP solution in my business, I bought two motherboards and two doutherboards from Ettus.I've installed it on my dual core pc, Linux FC5 x86_64 distribution. All the USRP tests works fine, everything seems to go goog, but I'm not able to start the GNUradi
When I set the decimation rate to 8 or less, that is <= 8Mhz bandwidth, and still use 8bit sample, it runs well.
So it may probably not be the problem as you said. But the degradation of SNR really cannot be ignored.
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Hi, all,
I've just found that the USRP can be configure to 8bit sample by the following code.
width = 8shift = 8format = self.u.make_format(width, shift)print "format =", hex(format)r = self.u.set_format(format)
And it is already in the usrp_fft.py and usrp_oscope.py.
So I g