hi @dream-math @jossevandelm @Julien
Thanks for some great collaboration, seems like there is significant community
interest in merging RISC-V support. Let's lay out some steps we can follow to
make this happen, and then we can discuss timelines.
1. To start with, I propose we explicitly tes
hi @Julien ,
With the help of @areusch , I have tried to make `tvm/tests/micro/qemu` work on
`qemu_riscv32`, and one month ago, it works for `test_compile_runtime` and
`test_relay` in `test_zephyr.py`, here is my
[code](https://github.com/Dream-math/Riscv-backend). But I find tvm code has
cha
Hi @Julien
Seems like we are working on a similar problem!
We have been actively trying to port TVM to our own accelerated RISC-V
microcontroller.
Check out:
https://discuss.tvm.apache.org/t/feedback-on-tvm-port-to-custom-accelerator/9548?u=jossevandelm
I'm also very interested in @areusch 's
Hi @areusch , Thanks a lot for your help!
I still have a question about the time needed: in your opinion, is it more a
1-month project or a 1-year project for a single person?
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You are rec
@areusch for step 2, if you also wanted to use TVM for the accelerator codegen
as well, would VTA provide a guide there? And would you still use BYOC there
(just calling out to TVM in BYOC for compilation as well)?
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hi @Julien,
Got it. TVM has two runtimes: a C++ runtime (used when OS present and
referenced in many of our tutorials) and a C runtime (used when OS not present;
referenced in our microTVM tutorials).
Support for this arrangement isn't complete yet but would fall under microTVM.
See the [µTV
Hi @areusch ,
There is no operating system on the RISC-V controller.
What is the difference between bare-metal and OS on the controller?
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hi @Julien ,
Do you have an operating system on the RISC-V controller?
Thanks,
Andrew
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Hi, I have a simple question: how much work time would it take for a single
Ph.D. student to bring TVM to a new CNN accelerator (RISC-V controller +
accelerator)?
Thanks in advance :slight_smile:
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r
