We are moving towards some unit tests to validate the plot output.
Such a test already exists for schematic plot output as a kicad-cli
test and will be expanded to PCB eventually.
But, even the recent changes such as
d5bd1f5aea042a238345171b99a195da9e0eab9e were entirely intentional and
not an acc
Thanks for the clarification Mark.
It would be nice if the development team informs about changes that will impact
in the plot generation. This could help people to know the changes are
intentional.
De: devlist@kicad.org en nombre de Mark Roszko
Enviado: sábado
