Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
is the backend flash driver.
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++
1 file changed, 10 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
b/OvmfPkg/RiscVVirt
There is no point to set satp to bare mode as that should be the
default mode when booting edk2.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
OvmfPkg/RiscVVirt/Sec/Memory.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
On Fri, Jul 14, 2023 at 3:24 AM Sunil V L wrote:
> On Fri, Jun 23, 2023 at 11:39:34AM -0700, Tuan Phan wrote:
> > During CpuDxe initialization, MMU will be setup with the highest
> > mode that HW supports.
> >
> > Reviewed-by: Andrei Warkentin
> > Signed-off
On Thu, Feb 23, 2023 at 3:55 PM Andrei Warkentin
wrote:
> RegisterCpuInterruptHandler did not allow setting
> exception handlers for anything beyond the timer IRQ.
> Beyond that, it didn't meet the spec around handling
> of inputs.
>
> RiscVSupervisorModeTrapHandler now will invoke
> set handlers
On Wed, Mar 1, 2023 at 8:59 PM Tuan Phan via groups.io wrote:
>
>
> On Thu, Feb 23, 2023 at 3:55 PM Andrei Warkentin <
> andrei.warken...@intel.com> wrote:
>
>> RegisterCpuInterruptHandler did not allow setting
>> exception handlers for anything beyond the tim
Reviewed-By: Tuan Phan
> On Jul 19, 2021, at 1:07 AM, Sunny Wang via groups.io
> wrote:
>
> This is to fix the SCT BS.AllocatePages failures (not found) with the
> case that the Start address is not aligned to 64k.
> For example,
> The following is available memo
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