Patch1: Added three PCDs for QemuFwCfgLibMmio
Patch2: Sparate QemuFwCfgLibMmio.c into two files and default as DXE
stage library.
Patch3: Added QemuFwCfgMmiLib PEI version
Patch4: Rename QemuFwCfgLibMmio.inf to QemuFwCfgMmioDxeLib.inf and
enable it in AARCH64 and RISCV64.
V1 -> V2:
1. Use HOBs i
Added a new GUID for QemuFwCfgLib MMIO version, called
gQemuFirmwareResourceHobGuid, which is used to save QEMU firmware
configure resource during PEI stage.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
Separate QemuFwCfgLibMmio.c into two files named QemuFwCfgLibMmio.c and
QemuFwCfgLibMmioDxe.c, added a new header named
QemuFwCfgLibMmioInternal.h for MMIO version.
Some DXE stage variables became non-static in this patch, they will be
restored to static in the next patch.
Build-tested only (with
Added the HOB methods to load and store the QEMU firmware configure
address, data address and DMA address, which are not enabled during the
DXE stage.
Build-tested only (with "ArmVirtQemu.dsc and RiscVVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc:
Added the PEI stage library for QemuFwCfgMmioLib, which uses the FDT to
find the fw_cfg and parse it.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Co-authored-by: Xianglai Li
Signed-off-by: Chao Li
---
.../Library/QemuFwCfgLib/Q
Copy QemuFwCfgLibMmio.inf to QemuFwCfgMmioDxeLib.inf,
QemuFwCfgLibMmio.inf will be deleted when all platforms switching is
completed.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
.../QemuFwCfgLib/QemuFw
Enable QemuFwCfgMmioDxeLib.inf in ArmVirtQemu.dsc and
ArmVirtQemuKernel.dsc.
Build-tested only (with "ArmVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Cc: Leif Lindholm
Cc: Sami Mujawar
Signed-off-by: Chao Li
---
Enable QemuFwCfgMmioDxeLib.inf in RiscVVirtQemu.dsc
Build-tested only (with "RiscVVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Cc: Sunil V L
Cc: Andrei Warkentin
Signed-off-by: Chao Li
---
OvmfPkg/RiscVVirt/Ris
All of platforms are switching to QemuFwCfgMmioDxeLib.inf, remove
QemuFwCfgLibMmio.inf now.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
.../Library/QemuFwCfgLib/QemuFwCfgLibMmio.inf | 54 --
Can you create PR for this patch? If it passes CI, I will add push label.
Thanks
Liming
> -邮件原件-
> 发件人: devel@edk2.groups.io 代表 Xianglei Cai
> 发送时间: 2024年4月25日 17:58
> 收件人: gaoliming ; devel@edk2.groups.io
> 抄送: Ni, Ray ; Lewandowski, Krzysztof
> ; Huang, Jenny ;
> Shih, More
> 主题: Re:
I have no access to push PR. But I tried with my personal fork, it can pass CI.
Thanks,
Xianglei
-Original Message-
From: gaoliming
Sent: Friday, April 26, 2024 4:44 PM
To: devel@edk2.groups.io; Cai, Xianglei
Cc: Ni, Ray ; Lewandowski, Krzysztof
; Huang, Jenny ; Shih,
More
Subject:
Felix and Sachin:
I don't find PI_SPECIFICATION_MINOR_REVISION definition from the latest
public PI 1.8A. So, this change may not be added now.
Thanks
Liming
> -邮件原件-
> 发件人: Sachin Ganesh
> 发送时间: 2024年4月25日 17:57
> 收件人: Felix Polyudov ; gaoliming
> ; devel@edk2.groups.io
> 抄送: zhiguan
Foster:
There is CI failure in https://github.com/tianocore/edk2/pull/5585. Please
resolve them first.
Thanks
Liming
> -邮件原件-
> 发件人: devel@edk2.groups.io 代表 gaoliming via
> groups.io
> 发送时间: 2024年4月23日 21:15
> 收件人: 'Nong, Foster' ; devel@edk2.groups.io;
> 'Kinney, Michael D' ; 'Chris L
PR: https://github.com/tianocore/edk2/pull/5546
Intel plans to separate the smbase relocation logic from
PiSmmCpuDxeSmm driver, and the related behavior will be
moved to the new interface defined by the SmmRelocationLib
class.
The SmmRelocationLib class provides the SmmRelocationInit()
interface
Intel plans to separate the smbase relocation logic from
PiSmmCpuDxeSmm driver, and the related behavior will be
moved to the new interface defined by the SmmRelocationLib
class.
The SmmRelocationLib class provides the SmmRelocationInit()
interface for platform to do the smbase relocation, which
s
This patch just separates the smbase relocation logic from
PiSmmCpuDxeSmm driver, and moves to the SmmRelocationInit
interface. It maintains the original implementation of most
functions and leaves the definitions of global variables
intact. Further refinements to the code are planned for
subsequen
This patch aims to rename global variables for clearer
association with Smm Init, ensuring their names are
distinct from those used in the PiSmmCpuDxeSmm Driver.
Cc: Ray Ni
Cc: Zeng Star
Cc: Gerd Hoffmann
Cc: Rahul Kumar
Signed-off-by: Jiaxin Wu
---
.../Library/SmmRelocationLib/Ia32/SmmInit.
Since SMM relocation is performed serially for each CPU, there is
no need to allocate buffers for all CPUs to store the SmBase
address in mSmBase and the Rebased flag in mRebased. A defined
global variable is sufficient.
This patch focuses on the mSmBase and mRebased global variables
to prevent un
This patch aims on mProcessorInfo global variable, which can be
defined as local variable in SmmRelocateBases(). With this patch,
no need to allocate the memory for all CPUs to store the
Processor Info.
Cc: Ray Ni
Cc: Zeng Star
Cc: Gerd Hoffmann
Cc: Rahul Kumar
Signed-off-by: Jiaxin Wu
---
.
This patch is to remove unnecessary CpuIndex.
Cc: Ray Ni
Cc: Zeng Star
Cc: Gerd Hoffmann
Cc: Rahul Kumar
Signed-off-by: Jiaxin Wu
---
UefiCpuPkg/Library/SmmRelocationLib/Ia32/Semaphore.c | 3 ---
.../Library/SmmRelocationLib/InternalSmmRelocationLib.h | 5 -
UefiCpuPkg/Lib
Due to the definition difference of SMRAM Save State,
SmmBase config in SMRAM Save State for AMD is also different.
This patch provides the AmdSmmRelocationLib library instance
to handle the SMRAM Save State difference.
Cc: Abdul Lateef Attar
Cc: Abner Chang
Cc: Ray Ni
Cc: Zeng Star
Cc: Gerd
There are below 2 differences between AMD & OVMF according
existing implementation:
1.The mode of the CPU check is different between the AMD & OVMF.
OVMF:
CpuSaveState->x86.SMMRevId & 0X
AMD:
LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA
2.Existing SmBase configuration is different be
In the PiSmmCpuDxeSmm driver, SMRAM allocation for SMI
handlers and processor Save State areas was traditionally
performed using the Smst->AllocatePages() function during
the DXE phase. The introduction of SmmRelocationLib
changes this process by moving the allocation to the PEI
phase, where Smst->
This patch refines the SmmAccess implementation:
1. SmramMap will be retrieved from the
gEfiSmmSmramMemoryGuid instead of original from
the TSEG Memory Base register.
2. Remove the gEfiAcpiVariableGuid creation, thus
the DESCRIPTOR_INDEX definition can be also cleaned.
3. The gEfiAcpiVariableGuid H
Based on gSmmBaseHobGuid:
If gSmmBaseHobGuid found, means SmBase info has been relocated
and recorded in the SmBase array.
So, this patch check smbase relocation is done or not in
SmmCpuFeaturesInitializeProcessor().
With SmmRelocationLib, gSmmBaseHobGuid will be always created.
Here this patch ju
This patch is to consume SmmRelocationInit for SmBase
Relocation.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Cc: Ray Ni
Signed-off-by: Jiaxin Wu
---
OvmfPkg/PlatformPei/Platform.c | 3 +
OvmfPkg/PlatformPei/Platform.h | 5 ++
OvmfPkg/Platfor
This patch just includes SmmRelocationLib in UefiPayloadPkg.
Cc: Guo Dong
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Cc: Ray Ni
Signed-off-by: Jiaxin Wu
Reviewed-by: Gua Guo
Reviewed-by: Guo Dong
---
UefiPayloadPkg/UefiPayloadPkg.dsc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Uef
This patch is to remove legacy SmBase relocation in
PiSmmCpuDxeSmm Driver. The responsibility for SmBase
relocation has been transferred to the SmmRelocationInit
interface, which now handles the following tasks:
1. Relocates the SmBase for each processor.
2. Generates the gSmmBaseHobGuid HOB.
As a
Reviewed-by: Gua Guo
From: Wu, Jiaxin
Sent: Friday, April 26, 2024 8:17:19 PM
To: devel@edk2.groups.io
Cc: Dong, Guo ; Rhodes, Sean ; Lu,
James ; Guo, Gua ; Ni, Ray
Subject: [PATCH v4 13/14] UefiPayloadPkg/UefiPayloadPkg.dsc: Include
SmmRelocationLib
This pa
On 4/25/24 01:58, Gerd Hoffmann wrote:
Hi,
That means the SMMRevId is 0_xx64h for AMD64 processor. But I am not
sure what the value is for AMD32 processor. Maybe 0 according to the
OVMF logic.
The smm emulation in the linux kernel uses 0 and 0x64.
But, I am very suspicious about the logi
For the most part, OVMF will clear the encryption bit for MMIO regions,
but there is currently one known exception during SEC when the APIC
base address is accessed via MMIO with the encryption bit set for
SEV-ES/SEV-SNP guests. In the case of SEV-SNP, this requires special
handling on the hypervis
On Fri, Apr 26, 2024 at 08:51:20AM -0500, Roth, Michael via groups.io wrote:
> For the most part, OVMF will clear the encryption bit for MMIO regions,
> but there is currently one known exception during SEC when the APIC
> base address is accessed via MMIO with the encryption bit set for
> SEV-ES/S
On Fri, 26 Apr 2024 at 16:16, Roth, Michael via groups.io
wrote:
>
> On Fri, Apr 26, 2024 at 08:51:20AM -0500, Roth, Michael via groups.io wrote:
> > For the most part, OVMF will clear the encryption bit for MMIO regions,
> > but there is currently one known exception during SEC when the APIC
> >
This adds an additional option to the dmem UEFI shell command for verbose
dumping of a couple of UEFI tables.
The tables specified are the RT Properties Table, the Image Execution Table,
and the Conformance Profiles table.
Supporting objects are added in the .inf and .uni files relating to Dmem
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4352
Implemented dumping of the Image Execution Table using Dmem.c
Cc: Ray Ni
Cc: Zhichao Gao
Signed-off-by: Sam Kaynor
Tested-by: Stuart Yoder
Reviewed-by: Stuart Yoder
Reviewed-by: Zhichao Gao
---
Notes:
v5:
- corrected comment
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4352
Implemented the dumping of the UEFI RT Properties Table using Dmem.c
Added new entry to the help command for the -verbose option
Cc: Ray Ni
Cc: Zhichao Gao
Signed-off-by: Sam Kaynor
Tested-by: Stuart Yoder
Reviewed-by: Stuart Yoder
Re
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4352
Adding support for EFI_CONFORMANCE_PROFILE_TABLE by adding an
associated header file and relevant GUIDs to MdePkg.dec as defined
in the UEFI 2.10 spec.
This table is needed to address changes being made within ShellPkg.
Cc: Michael D Kinney
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4352
Implemented dumping of the UEFI Conformance Profiles Table using Dmem.c
Uses header file for GUIDs added in previous patch
Cc: Ray Ni
Cc: Zhichao Gao
Signed-off-by: Sam Kaynor
---
Notes:
v6:
- Moved MdePkg changes to separate pa
For the most part, OVMF will clear the encryption bit for MMIO regions,
but there is currently one known exception during SEC when the APIC
base address is accessed via MMIO with the encryption bit set for
SEV-ES/SEV-SNP guests. In the case of SEV-SNP, this requires special
handling on the hypervis
On Fri, Apr 26, 2024 at 05:25:15PM +0200, Ard Biesheuvel wrote:
> On Fri, 26 Apr 2024 at 16:16, Roth, Michael via groups.io
> wrote:
> >
> > On Fri, Apr 26, 2024 at 08:51:20AM -0500, Roth, Michael via groups.io wrote:
> > > For the most part, OVMF will clear the encryption bit for MMIO regions,
>
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