Hello,
Just a ping for the patch-set,
Regards,
Pierre
On 5/9/23 09:40, PierreGondois via groups.io wrote:
From: Pierre Gondois
This patchset follows the 'code first' approach and relies on [1].
This patchset follows the thread at [3] that aims to solve [2].
[1] and [2] are bound and this patc
W dniu 5.06.2023 o 08:37, Marcin Juszkiewicz via groups.io pisze:
This changeset was supposed to add SVE/SME information but got some
updates to improve output of ArmCpuInfo application a bit too.
Probably would need to definition of system registers for older
toolchains.
Changes since v1:
- sh
Hi Oliver,
I see the PR you linked is marked as draft and test.
I'm happy to help push this if you can confirm when you're done testing.
Thanks,
Michael
On 6/22/2023 7:37 AM, Oliver Steffen wrote:
Use the latest Linux container image (from 2023-05-30).
It uses Qemu 8.0.0 and gcc 12.
REF: htt
Automatically set the nxcompat flag in the DLL Characteristics field of
the Optional Header of the PE32+ image. For this flag to be set
automatically, it must, the section alignment must be evenly divisible
by 4K (EFI_PAGE_SIZE) and no section must be executable and writable.
Cc: Rebecca Cran
Cc:
Utilize GenFw to automatically set the NXCOMPAT bit of the DLL Characteristics
field of the Optional Header if the following requirements are met:
1. It is a 64bit PE
2. The section alignment is evently divisible by 4K
3. No section is both EFI_IMAGE_SCN_MEM_EXECUTE and EFI_IMAGE_SCN_MEM_WRITE
C
Add the bit masks for DLL Characteristics, used within the optional
header of a PE, to the PeImage.h header file.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Joey Vagedes
---
MdePkg/Include/IndustryStandard/PeImage.h | 15 +++
1 file changed, 15 insertions(
On Fri, 23 Jun 2023 at 18:03, Joey Vagedes wrote:
>
> Utilize GenFw to automatically set the NXCOMPAT bit of the DLL Characteristics
> field of the Optional Header if the following requirements are met:
>
> 1. It is a 64bit PE
> 2. The section alignment is evently divisible by 4K
> 3. No section i
On Tue, 20 Jun 2023 at 19:07, Sean Brogan wrote:
>
> I don't think a MemoryAttributes2Protocol with a single API would have
> avoided the errors.
>
> The programming pattern that triggered this would still need multiple calls
> to any API and in the future where all memory is allocated as NX thi
On Wed, 21 Jun 2023 at 09:31, Corvin Köhne wrote:
>
> CI: https://github.com/tianocore/edk2/pull/4545
>
> Corvin Köhne (6):
> OvmfPkg/Library: fix definition of GetAcpiRsdpFromMemory
> OvmfPkg: avoid including AcpiPlatformLib twice
> OvmfPkg: move PciEncoding into AcpiPlatformLib
> OvmfPkg
On Mon, 19 Jun 2023 at 13:54, Corvin Köhne wrote:
>
> Bhyve will gain support for TPM emulation in the near future. Therefore,
> prepare OVMF by copying all TPM driver used by qemu's OVMF DSC into the
> bhyve OVMF DSC.
>
> Signed-off-by: Corvin Köhne
> Reviewed-by: Rebecca Cran
> Acked-by: Gerd
This series adds MMU support for RISC-V. Only SV39/48/57 modes
are supported and tested. The MMU is required to support setting
page attribute which is the first basic step to support security
booting on RISC-V.
There are two parts:
1. Add MMU base library. MMU will be enabled during
CpuDxe initia
Add an API to retrieve satp register value.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
MdePkg/Include/Library/BaseLib.h | 5 +
MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8
2 files changed, 13 insertions(+)
diff --git a/MdePkg/Incl
The satp mode bits shift is used cross modules. It should be defined
in one place.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/MdePkg
The size should be for single region, not the whole firmware FD.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
.../Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c| 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/OvmfPkg/RiscV
Normally, DXE driver would add device resource to GCD before start using.
But some key resources such as uart used for printing info at very early
stage.
Those resources should be populated to HOB in SEC phase so they are
added to GCD before MMU enabled.
Signed-off-by: Tuan Phan
Reviewed-by: And
Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
is the backend flash driver.
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++
1 file changed, 10 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fd
There is no point to set satp to bare mode as that should be the
default mode when booting edk2.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
OvmfPkg/RiscVVirt/Sec/Memory.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --gi
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Reviewed-by: Andrei Warkentin
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
I think that is an interesting idea but I would expect some push back
from OS loader maintainers. I would expect they don't want to be
constrained by the lowest common capabilities of the platforms they
still support/run on in the ecosystem. Not to mention the challenges
around servicing and/
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