Remove system level cache (SLC) entry from ACPI PPTT table. SLC on the
Neoverse reference design platforms is the memory side cache and so it
is removed from PPTT table.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 4 +---
Platform/ARM/SgiPkg/AcpiTables/
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3828
This is a bugfix of
bf9230a9f3dde065c3c8b4175ccd32e44e8f0362.
1.In the current code, gPlatformFinalPcd will save all PCDs used at
whole compile process, which wastes runtime memory and is unnecessary.
This patch makes gPlatformFinalPcd sav
Hi Abner,
I see, the C Coding Standards Spec tells us that "macro guard" should be like
"ifndef PROCESSOR_BIND_H_", but there is very little attention in the current
edk2 repo. Anyway, I will fix it in the next version.
--
Thanks,
Chao
On 4月 16 2022, at 10:58 晚上, "Abne
Changes since V1:
- Rebased on top of latest master branch.
- Rebased on top of patch to remove SLC cache entries from PPTT (link
for the same in edk2.groups.io is provided below)
Arm infrastructure reference design platforms uses ACPI tables to
provide the hardware information to the operating
Update the SGI-575 platform specific ACPI tables to ACPI version v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc | 105 +++-
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 86
2 files changed, 100 insertions(+), 91 deleti
Update the common ACPI tables used by all the Neoverse Reference Design
platforms to ACPI version v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 219 ++--
Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc| 30 +--
Platform/ARM/SgiPkg/AcpiTables/Fa
Update the Rd-N1-Edge platform specific ACPI tables to ACPI version
v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc | 105 +++-
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 88
2 files changed, 101 insertions(+), 92
Update the Rd-N1-Edge multichip platform specific ACPI tables to ACPI
version v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc | 52 ---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc | 151 ++--
Platform/ARM/SgiPkg/AcpiTables/Rd
Update the Rd-E1-Edge platform specific ACPI tables to ACPI version
v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc | 247 ++--
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 106 -
2 files changed, 181 insertions(+), 172 delet
Update the Rd-V1 platform specific ACPI tables to ACPI version v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc | 159 ++--
Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 77 +-
2 files changed, 122 insertions(+), 114 deletions(-)
dif
Update the Rd-N2 platform specific ACPI tables to ACPI version v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc | 163 ++--
Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 77 -
2 files changed, 124 insertions(+), 116 deletions(-)
diff
Update the Rd-V1 multichip platform specific ACPI tables to ACPI version
v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc | 64
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc | 165 ++--
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.as
Update the Rd-N2-Cfg1 platform specific ACPI tables to ACPI version
v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 112 ++--
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 73 ++---
2 files changed, 93 insertions(+), 92 del
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3679
This dependency is needed to build openssl lib with ECC ciphers
under IA32 Windows and adds implementation for _allmul and _allshr
instrinsics.
It is taken from Project Mu:
microsoft/mu_basecore@b55b341
Signed-off-by: yi1 li
---
.../Libra
As subject.
yi1 li (4):
CryptoPkg: Add instrinsics to support building ECC on IA32 windows
CryptoPkg: Reconfigure OpensslLib to add EC algorithms
CryptoPkg: Make EC source file config-able
CryptoPkg: Add PcdEcEnabled to Base/Pei/SmmCryptLib.inf
CryptoPkg/CryptoPkg.dec
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3679
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3828
Reconfigure OpensslLib to add elliptic curve cipher algorithms.
Signed-off-by: yi1 li
---
.../Library/Include/openssl/opensslconf.h | 3 --
CryptoPkg/Library/OpensslLib/OpensslLi
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3679
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3828
Base/Pei/SmmCryptLib.inf will use openssllib, and the header file
opensslconf.h in openssllib will use PCD, but it is not declared in
the inf file, which will cause warnings in some comp
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3679
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3828
Use PCD gEfiCryptoPkgTokenSpaceGuid.PcdEcEnabled to config-able
source files list in OpensslLib.inf and OpensslLibCrypto.inf.
If PcdEcEnabled equals to FALSE, this file will not be compi
On 4/16/22 19:56, Xu, Min M wrote:
On April 16, 2022 11:09 PM, Lendacky, Thomas wrote:
On 4/15/22 20:57, Xu, Min M wrote:
On April 16, 2022 4:52 AM, Lendacky, Thomas wrote:
Unfortunately, this driver also breaks SEV-ES. I bypassed the TDX
code in the SEC library, but then hit an issue because
On 4/16/22 22:01, Min Xu wrote:
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3902
The confidential computing guest type (GUEST_TYPE) was defined in
OvmfPkg/Include/WorkArea.h. Now it is to be moved to
MdePkg/Include/ConfidentialComputingGuestAttr.h and renamed as
CC_GUEST_TYPE.
There are
On April 18, 2022 9:48 PM, Tom Lendacky wrote:
> > +//
> > +// Confidential computing guest type
> > +//
> > +typedef enum {
> > + CCGuestTypeNonEncrypted = 0,
> > + CCGuestTypeAmdSev,
> > + CCGuestTypeIntelTdx,
> > +} CC_GUEST_TYPE;
>
> Should these be CcGuest... ? The precedent seems to be us
On Mon, Apr 18, 2022 at 01:14 AM, Pranav Madhu wrote:
>
> Remove system level cache (SLC) entry from ACPI PPTT table. SLC on the
> Neoverse reference design platforms is the memory side cache and so it
> is removed from PPTT table.
>
> Signed-off-by: Pranav Madhu
> ---
> Platform/ARM/SgiPkg/Inc
On 4/16/22 22:01, Min Xu wrote:
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3902
CcProbeLib is imported in BaseIoLibIntrinsicSev.
OvmfPkg/Library/CcProbeLib is the OvmfPkg version which checks
OvmfWorkArea to return the Cc guest type. It is included
in OvmfPkgX64.dsc and IntelTdx/IntelTdx
A new top level PCD should not be added.
There is already a structured PCD to enable/disable crypto features.
We take advantage of compiler optimizations to remove unused functions,
so filtering the source files using a PCD should not be required.
I want to make sure we use a consistent method t
There are other patch series to move intrinsics to the MdePkg for
OpenSSL 3.0 enabling.
I recommend you work with Gerd on the intrinsic topic.
Mike
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of yi1 li
> Sent: Monday, April 18, 2022 6:03 AM
> To: devel@edk2.groups.io
> C
On 4/16/22 22:01, Min Xu wrote:
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3902
Bad IO performance in SEC phase is observed after TDX features was
introduced. (after commit b6b2de884864 - "MdePkg: Support mmio for
Tdx guest in BaseIoLibIntrinsic").
This is because IsTdxGuest() will be c
Hi,
Did you evaluate the use of the following PCD to make an SEC version?
## Enable/Disable the families and individual services produced by the
# EDK II Crypto Protocols/PPIs. The default is all services disabled.
# This Structured PCD is associated with PCD_CRYPTO_SERVICE_FAMILY_ENABLE
On 4/15/22 23:23, Desimone, Nathaniel L wrote:
Hi Marvin,
-Original Message-
From: Marvin Häuser
Sent: Friday, April 15, 2022 9:44 AM
To: disc...@edk2.groups.io; Johnson, Brian ;
Desimone, Nathaniel L ; Andrew Fish
; devel@edk2.groups.io
Cc: Pedro Falcato ; adachristin...@gmail.com;
Sh
On 4/18/22 12:54, Pranav Madhu via groups.io wrote:
Changes since V1:
- Rebased on top of latest master branch.
- Rebased on top of patch to remove SLC cache entries from PPTT (link
for the same in edk2.groups.io is provided below)
Arm infrastructure reference design platforms uses ACPI tab
Hi, Devel:
We would like to build a code for perf but facing a error as below,
Please help give some suggestion to us , thanks a lot.
BIOS version: 004000_ULTRON.
-
build.py...
: error C0DE: Unknown fatal er
*Tools, CI, Code base construction meeting series*
*When:*
04/18/2022
4:30pm to 5:30pm
(UTC-07:00) America/Los Angeles
*Where:*
https://github.com/tianocore/edk2/discussions/2614
View Event ( https://edk2.groups.io/g/devel/viewevent?eventid=1467817 )
*Description:*
TianoCore community,
Micros
From: Michael Kubacki
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3478
Adds support for getting the variable flash information from
VariableFlashInfoLib. This library abstracts the source of flash
information so platforms could expect the information to come
from a different source in the
On April 18, 2022 11:27 PM, Lendacky, Thomas wrote:
> After working around the PCI library issue (for which Min will be submitting a
> patch), this series boots successfully for SEV, SEV-ES and SEV-SNP when built
> as X64. I documented the issue that SEV has with
> Ia32X64 in patch 5/7 and I'll hav
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3902
Bad IO performance in SEC phase is observed after TDX features was
introduced. (after commit b6b2de884864 - "MdePkg: Support mmio for
Tdx guest in BaseIoLibIntrinsic").
This is because IsTdxGuest() will be called in each MMIO operation.
It i
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3902
The confidential computing guest type (GUEST_TYPE) was defined in
OvmfPkg/Include/WorkArea.h. Now it is to be moved to
MdePkg/Include/ConfidentialComputingGuestAttr.h and renamed as
CC_GUEST_TYPE.
There are 2 reasons for this change.
1. CC_G
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3902
Replace GUEST_TYPE with CC_GUEST_TYPE which is defined in
MdePkg/Include/ConfidentialComputingGuestAttr.h.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: James Bottomley
Cc: Jiewen Yao
Cc: Gerd Hoffmann
Cc: Brijesh Singh
Cc:
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3902
CcProbeLib is used to probe the Confidential Computing guest type.
This library is designed to run on SEC / PEI / DXE phases. A null
instance of the library always returns CCGuestTypeNonEncrypted.
A platform specific CcProbeLib will be implem
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3902
This is the OvmfPkg specific CcProbeLib. It checks the Ovmf WorkArea
(PcdOvmfWorkAreaBase) to return the guest type.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: James Bottomley
Cc: James Bottomley
Cc: Jiewen Yao
Cc: Gerd H
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3902
CcProbeLib is imported in BaseIoLibIntrinsicSev.
OvmfPkg/Library/CcProbeLib is the OvmfPkg version which checks
OvmfWorkArea to return the Cc guest type. It is included
in OvmfPkgX64.dsc and IntelTdx/IntelTdxX64.dsc.
Other .dsc include the M
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3902
Bad IO performance in SEC phase is observed after TDX features was
introduced. (after commit b6b2de884864 - "MdePkg: Support mmio for
Tdx guest in BaseIoLibIntrinsic").
This is because IsTdxGuest() will be called in each MMIO operation.
It i
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3902
TdIsEnabled() uses the CPUID instruction. At this point, exception
handling is not established and a CPUID instruction will generate
a #VC and cause the booting guest to crash.
CcProbe() checks Ovmf work area to return the guest type. So cal
Hi
I am confused.
This patch set has already been merged. Why it is sent again?
Have you rebased to latest tree, before you send out patch?
Thank you
Yao Jiewen
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of yi1 li
> Sent: Monday, April 18, 2022 9:03 PM
> To: devel@ed
The ObjCopyFlag and EntryOutputDir need to be modified when
building IA32 UniversalPayload Entry
Signed-off-by: Dun Tan
Cc: Ray Ni
Cc: Guo Dong
Cc: Benjamin You
Cc: Zhiguang Liu
---
UefiPayloadPkg/UniversalPayloadBuild.py | 18 --
1 file changed, 12 insertions(+), 6 deletions
Hi Mike,
This is a wrong email sequence due to my mishandling, sorry for confusing,
please ignore this patch.
-Original Message-
From: Kinney, Michael D
Sent: Monday, April 18, 2022 11:24 PM
To: devel@edk2.groups.io; Li, Yi1 ; Gerd Hoffmann
; Kinney, Michael D
Subject: RE: [edk2-deve
Thanks Min.
Merged - https://github.com/tianocore/edk2/pull/2790
> -Original Message-
> From: Xu, Min M
> Sent: Tuesday, April 19, 2022 8:26 AM
> To: devel@edk2.groups.io
> Cc: Xu, Min M ; Kinney, Michael D
> ; Gao, Liming ; Liu,
> Zhiguang ; James Bottomley ;
> Yao, Jiewen ; Gerd Hoffma
BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Groups.io Inc//Groups.io Calendar//EN
METHOD:PUBLISH
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-PUBLISHED-TTL:PT1H
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
LAST-MODIFIED:20220317T223602Z
TZURL:http://tzurl.org/zoneinfo-outlook/America/Los_Angeles
From: Michael Kubacki
https://bugzilla.tianocore.org/show_bug.cgi?id=3905
Fixes GCC compilation errors in DxePrmContextBufferLibUnitTest.c.
Cc: Michael Kubacki
Cc: Nate DeSimone
Cc: Ankit Sinha
Signed-off-by: Michael Kubacki
---
PrmPkg/Library/DxePrmContextBufferLib/UnitTest/DxePrmContext
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3904
TdxDxe driver is introduced for Intel TDX feature. Unfortunately, this
driver also breaks boot process in SEV-ES guest. The root cause is in
the PciLib which is imported by TdxDxe driver.
In a SEV-ES guest the AmdSevDxe driver performs a
Mem
Hi
If TdxDxe breaks SEV, should we skip the TdxDxe in SEV path?
I don't understand why we need use Cfg8.
Thank you
Yao Jiewen
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Min Xu
> Sent: Tuesday, April 19, 2022 9:58 AM
> To: devel@edk2.groups.io
> Cc: Xu, Min M ; Brije
On April 19, 2022 10:08 AM, Yao Jiewen wrote:
>
> If TdxDxe breaks SEV, should we skip the TdxDxe in SEV path?
>
> I don't understand why we need use Cfg8.
>
In TdxDxe driver we need to relocate APs and it requires the TdxMailboxLib.
The lib chain is that TdxMailbox -> SynchronizationLib -> Ti
Why does TdxDxe call TdxMailbox in an SEV platform?
Or why does TdxMailbox call SynchronizationLib in an SEV platform?
There are many places we can do CcProbe to stop action. Why we need do it in
DSC?
In general, DSC lib override should be the last option, because it requires the
platform integ
Reviewed-by: Ray Ni
> -Original Message-
> From: Tan, Dun
> Sent: Tuesday, April 19, 2022 8:51 AM
> To: devel@edk2.groups.io
> Cc: Ni, Ray ; Dong, Guo ; You, Benjamin
> ; Liu,
> Zhiguang
> Subject: [PATCH] UefiPayloadPkg: Fix IA32 entry build failure
>
> The ObjCopyFlag and EntryOutpu
On April 19, 2022 10:54 AM, Yao Jiewen wrote:
>
> Why does TdxDxe call TdxMailbox in an SEV platform?
> Or why does TdxMailbox call SynchronizationLib in an SEV platform?
>
TdxDxe will not call TdxMailbox/SynchronizationLib in SEV platform. The problem
is in the lib constructor. When TdxDxe drive
Do you mean, with SEV introduced, OVMF cannot use PCI express any more?
Thank you
Yao Jiewen
> -Original Message-
> From: Xu, Min M
> Sent: Tuesday, April 19, 2022 11:05 AM
> To: Yao, Jiewen ; devel@edk2.groups.io
> Cc: Brijesh Singh ; Aktas, Erdem
> ; James Bottomley ; Tom
> Lendacky
In AmdSevDxe's entry point it clears the C-bit from PcdPciExpressBaseAddress
and other memory spaces if needed. Please see
https://github.com/tianocore/edk2/blob/master/OvmfPkg/AmdSevDxe/AmdSevDxe.c#L81-L95.
After that OVMF can use PCI express.
This broken is caused by the call sequence of TdxD
Hi Sean and Bret,
I prepare submit a new architecture code to edk2, and I have applied for an
Azure ID. There have two questions when trigger the Azure CI, please refer to
the following two links:
https://dev.azure.com/kilaterlee/LoongArch_edk2/_build/results?buildId=31&view=logs&j=9701361e-254
Can SEV clear the C-bit in SEC phase?
I think that is right way to ensure PCI Express can always be accessed by
anyone.
> -Original Message-
> From: Xu, Min M
> Sent: Tuesday, April 19, 2022 12:39 PM
> To: Yao, Jiewen ; devel@edk2.groups.io
> Cc: Brijesh Singh ; Aktas, Erdem
> ; James
OK. Let me describe what I think.
PCI Express BAR need to be initialized by someone in the platform.
This initialization may require CFG8. That is understandable.
A good design is that: After the PCIE BAR is initialized, it can be accessed.
Requires additional step (such as clear C-bit) means the
Hi Liming, Mike,
Can you help to create the PR of these patch set? This is the first patch and
the second one is ShellPkg with the same titile.
Thanks,
Zhichao
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of
> gaoliming
> Sent: Sunday, April 17, 2022 11:25 AM
> To: devel
Hi,
> As the first step CC_GUEST_TYPE is defined in this patch. In the
> next patch GUEST_TYPE will be deleted. This is to make sure the
> bisect work correctly.
Hmm, what exactly went wrong? Splitting into two patches looks
pointless. If the change is too big for an all-in-one patch typical
Hi Pu,
When would you expect having CpuLib merged to edk2 mainstream?
Regards,
Abner
From: devel@edk2.groups.io on behalf of Abner Chang
Sent: Friday, April 1, 2022 9:45 PM
To: devel@edk2.groups.io ; yu...@intel.com
Subject: Re: [edk2-devel] [PATCH v1 00/15] Me
On Mon, Apr 18, 2022 at 07:59:56AM +0800, Min Xu wrote:
> RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853
>
> TdHobList and Configuration FV are external data provided by Host VMM.
> These are not trusted in Td guest. So they should be validated , measured
> and extended to Td RTMR regist
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