This series brings support for building PlatformStandaloneMmRpmb for
32bit Arm architectures. This series is based on series [1] in edk2
that allows to build StandaloneMm package for 32bit Arm. This series
starts by syncing with paths changes from [1] series, then comes
changes for Arm 32bit suppor
Build PlatformStandaloneMmRpmb for ARM architecture (32bit arm machine).
The generated image targets an execution environment similar to AArch64
StMM secure partition in OP-TEE but in 32bit mode.
GCC flag -fno-stack-protector
added. The stack protection code bring
GOT dependencies we prefer avoid
Add SMCCC function IDs for RPMB read/write service on 32bit architectures.
Define generic SP_SVC_RPMB_READ/SP_SVC_RPMB_WRITE IDs for native target
architecture (32b or 64b).
Changes OpTeeRpmbFvb.c to use architecture agnostic macro
ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ for 32b and 64b support.
Cc: A
Use (UINTN) cast to cast physical or virtual address values to the
pointer size before casting from/to a pointer value.
Cc: Ard Biesheuvel
Cc: Ilias Apalodimas
Cc: Leif Lindholm
Cc: Sami Mujawar
Signed-off-by: Etienne Carriere
---
Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.c | 21 +-
Synchronize with edk2 package where StandaloneMmCpu component has moved
from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.inf
to StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.inf
Cc: Ard Biesheuvel
Cc: Ilias Apalodimas
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Sughosh
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3384
Currently, UefiBootManagerLib has the below assumption:
Assume the BootManagerMenuFile is in the same FV as the module links to this
library.
It has some limitation now, so remove the assumption.
Cc: Jian J Wang
Cc: Hao A Wu
Cc: Zhicha
From: Nicola Mazzucato
The SCP-firmware has moved to full support for SCMIv2 which means that
the base protocol can be either compliant with SCMI v1 or v2.
Allow any version between SCMI v1.0 and SCMI v2.0 to be compatible
with the current implementation.
Signed-off-by: Nicola Mazzucato
Signed
Hi Ard,
On 5/7/21 6:33 PM, Ard Biesheuvel wrote:
> Hello Pierre,
>
> On Thu, 6 May 2021 at 12:43, wrote:
>> From: Nicola Mazzucato
>>
>> The SCP-firmware has moved to full support for SCMIv2 which means that
>> the base protocol can be either compliant with SCMI v1 or v2.
>>
>> Allow any version
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of
> Zhiguang Liu
> Sent: Monday, May 10, 2021 4:16 PM
> To: devel@edk2.groups.io
> Cc: Wang, Jian J ; Wu, Hao A ;
> Gao, Zhichao ; Ni, Ray
> Subject: [edk2-devel] [PATCH] MdeModulePkg: Retrive boot manager menu
> from any fv
>
Hi Pranav,
Please find my response inline marked [SAMI].
Regards,
Sami Mujawar
On 28/04/2021 01:12 PM, Pranav Madhu wrote:
Add helper macros for the creation for PPTT table. These macros help
with initializing processor hierarchy node structure, cache type
structure and ID structure.
Signed-
Hi Pranav,
Please see my response inline marked [SAMI].
Regards,
Sami Mujawar
On 28/04/2021 01:12 PM, Pranav Madhu wrote:
From: Pranav Madhu
The SGI-575 platform includes two clusters with four single-thread CPUs.
Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache
and 5
Hi All,
I have tested this patch on Juno R2.
Tested-by: Sami Mujawar
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 10/05/2021, 09:26, "pierre.gond...@arm.com" wrote:
From: Nicola Mazzucato
The SCP-firmware has moved to full support for SCMIv2 which means that
the base p
Hi Hao,
I don't have the data about the boot performance.
However, I think it has little impact for the originally working platforms.
In function GetSectionFromAnyFv, It will first search section in current FV.
If it finds the section, it will return succuss.
Only if it can't find the section, i
Reviewed-by: Heng Luo
> -Original Message-
> From: Chuang, SofiaX
> Sent: Tuesday, May 4, 2021 2:22 AM
> To: devel@edk2.groups.io
> Cc: Chuang, SofiaX ; Chaganty, Rangasai V
> ; Desimone, Nathaniel L
> ; Luo, Heng
> Subject: [edk2-devel][PATCH v4 2/7]
> TigerlakeOpenBoard: Move ReportCp
As per ACPI 6.3 specification, the DSDT/SSDT table should use revision 2
, so update the revision numbers to 2.
This also fixes https://github.com/pftf/RPi4/issues/94 (FWTS failures).
Testing Done:
- Booted to UEFI Shell and used apciview command to check all ACPI
tables' revision.
- Ran F
Hi Pranav,
Please find my response inline marked [SAMI].
Regards,
Sami Mujawar
On 28/04/2021 01:35 PM, Pranav Madhu wrote:
The SGI-575 platform includes two clusters with four single-thread CPUs.
Add processor container devices for the two clusters on the SGI-575
platform and move the existi
Hi Pranav,
Please find my response inline marked [SAMI].
Regards,
Sami Mujawar
On 28/04/2021 01:35 PM, Pranav Madhu wrote:
Add helper macros required for use with ACPI collaborative processor
performance control (CPPC). This patch adds macros for initializing ACPI
_CPC and _PSD control metho
Hi Pranav,
Is it possible to send the PPTT table dump using ACPIview for these
platforms, please?
Shell> acpiview -s PPTT
Regards,
Sami Mujawar
On 28/04/2021 01:12 PM, Pranav Madhu wrote:
Changes since V1:
- Rebase the patches on top of latest master branch
- Addressed comments from Pierre
Looks good. However, I'm thinking about if this is a UEFI specification issue.
It looks like we should change the parameter type in
EFI_SIMPLE_TEXT_OUTPUT_MODE data structure instead of doing typecasting.
Morevover, we may also need to check the files below:
-
uefi-sct\SctPkg\TestCase\UEF
On 5/10/21 11:24 AM, Sunny Wang wrote:
Looks good. However, I'm thinking about if this is a UEFI specification issue.
It looks like we should change the parameter type in
EFI_SIMPLE_TEXT_OUTPUT_MODE data structure instead of doing typecasting.
Morevover, we may also need to check the files belo
On 2021.05.10 10:08, Sunny Wang wrote:
As per ACPI 6.3 specification, the DSDT/SSDT table should use revision 2
, so update the revision numbers to 2.
This also fixes https://github.com/pftf/RPi4/issues/94 (FWTS failures).
Testing Done:
- Booted to UEFI Shell and used apciview command to chec
Hi Rebecca
+Tom
On 05/08/21 21:47, Rebecca Cran wrote:
> I'm setting up a new Jenkins server to do Bhyve builds and run on
> platforms that aren't currently tested with the GitHub/Azure system.
>
> Since VS2012 appears to be a supported toolchain, I tried building
> OvmfPkgX64 with it (I'm also
On 05/09/21 19:42, Rebecca Cran wrote:
> Similarly the build is also failing with GCC49, using gcc 4.9.2:
>
> /edk2/ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.c: In
> function 'ShellSortFileList':
> Building ...
> /edk2/OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf [X64]
On 5/10/21 5:56 AM, Laszlo Ersek wrote:
Hi Rebecca
+Tom
On 05/08/21 21:47, Rebecca Cran wrote:
I'm setting up a new Jenkins server to do Bhyve builds and run on
platforms that aren't currently tested with the GitHub/Azure system.
Since VS2012 appears to be a supported toolchain, I tried build
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3385
A VS2012 build fails with a cast conversion warning when the SEV-ES work
area PCD is cast as a pointer to the SEV_ES_AP_JMP_FAR type.
When casting from a PCD value to a pointer, the cast should first be done
to a UINTN and then to the pointe
On Mon, 10 May 2021 at 13:13, Pete Batard wrote:
>
> On 2021.05.10 10:08, Sunny Wang wrote:
> > As per ACPI 6.3 specification, the DSDT/SSDT table should use revision 2
> > , so update the revision numbers to 2.
> > This also fixes https://github.com/pftf/RPi4/issues/94 (FWTS failures).
> >
> > Te
On Mon, 10 May 2021 at 10:51, Sami Mujawar wrote:
>
> Hi All,
>
> I have tested this patch on Juno R2.
>
> Tested-by: Sami Mujawar
> Reviewed-by: Sami Mujawar
>
Merged as #1630
Thanks all.
>
> On 10/05/2021, 09:26, "pierre.gond...@arm.com"
> wrote:
>
> From: Nicola Mazzucato
>
>
On Wed, 5 May 2021 at 04:10, Yao, Jiewen wrote:
>
> Acked-by: Jiewen Yao
>
> Need ARM expert to comment if it is OK to refer AArch64 for ARM?
>
This looks fine to me.
>
> > -Original Message-
> > From: devel@edk2.groups.io On Behalf Of Etienne
> > Carriere
> > Sent: Tuesday, May 4, 20
On Tue, 4 May 2021 at 17:20, Etienne Carriere
wrote:
>
> Change GenFv for Arm architecture to generate a specific jump
> instruction as image entry instruction, when the target entry label
> is assembled with Thumb instruction set. This is possible since
> SecCoreEntryAddress value fetched from th
On Mon, 10 May 2021 at 09:53, Etienne Carriere
wrote:
>
> This series brings support for building PlatformStandaloneMmRpmb for
> 32bit Arm architectures. This series is based on series [1] in edk2
> that allows to build StandaloneMm package for 32bit Arm. This series
> starts by syncing with paths
On Fri, 30 Apr 2021 at 20:04, Marcin Wojtas wrote:
>
> Hi,
>
>
> pon., 19 kwi 2021 o 10:52 Marcin Wojtas napisał(a):
> >
> > pon., 19 kwi 2021 o 10:49 Marcin Wojtas napisał(a):
> > >
> > > Hi,
> > >
> > > This series applies modifications to the MMC settings
> > > on the platforms based on the M
pon., 10 maj 2021 o 18:07 Ard Biesheuvel napisał(a):
>
> On Fri, 30 Apr 2021 at 20:04, Marcin Wojtas wrote:
> >
> > Hi,
> >
> >
> > pon., 19 kwi 2021 o 10:52 Marcin Wojtas napisał(a):
> > >
> > > pon., 19 kwi 2021 o 10:49 Marcin Wojtas napisał(a):
> > > >
> > > > Hi,
> > > >
> > > > This series
Adding Ard's new e-mail
From: devel@edk2.groups.io On Behalf Of Andrei Warkentin
via groups.io
Sent: Friday, April 30, 2021 4:30 PM
To: Jeremy Linton ; devel@edk2.groups.io
Cc: Ard Biesheuvel ; l...@nuviainc.com; p...@akeo.ie;
Samer El-Haj-Mahmoud
Subject: Re: [edk2-devel] [PATCH 0/3] SD+USB p
Adding Ard's new e-mail address
From: devel@edk2.groups.io On Behalf Of Samer
El-Haj-Mahmoud via groups.io
Sent: Friday, April 30, 2021 2:28 PM
To: Andrei Warkentin (awarken...@vmware.com) ; Jeremy
Linton ; devel@edk2.groups.io
Cc: Ard Biesheuvel ; l...@nuviainc.com; p...@akeo.ie;
Samer El-Haj
+ Ard's new e-mail address
> -Original Message-
> From: Jeremy Linton
> Sent: Thursday, April 8, 2021 1:59 AM
> To: devel@edk2.groups.io
> Cc: Ard Biesheuvel ; l...@nuviainc.com;
> p...@akeo.ie; Samer El-Haj-Mahmoud mahm...@arm.com>; Andrei Warkentin (awarken...@vmware.com)
> ; Jeremy Li
+ Ard’s new e-mail address
> -Original Message-
> From: Pete Batard
> Sent: Thursday, April 8, 2021 5:48 AM
> To: Jeremy Linton ; devel@edk2.groups.io
> Cc: Ard Biesheuvel ; l...@nuviainc.com; Samer
> El-Haj-Mahmoud ; Andrei Warkentin
> (awarken...@vmware.com)
> Subject: Re: [PATCH 1/3]
+ Ard's new e-mail address
From: Andrei Warkentin
Sent: Thursday, April 8, 2021 10:18 AM
To: Pete Batard ; Jeremy Linton ;
devel@edk2.groups.io
Cc: Ard Biesheuvel ; l...@nuviainc.com; Samer
El-Haj-Mahmoud
Subject: Re: [PATCH 1/3] Platform/RaspberryPi/Acpitables: Enable Arasan hispeed
mode
R
+ Ard's new e-mail address
> -Original Message-
> From: Jeremy Linton
> Sent: Thursday, April 8, 2021 1:59 AM
> To: devel@edk2.groups.io
> Cc: Ard Biesheuvel ; l...@nuviainc.com;
> p...@akeo.ie; Samer El-Haj-Mahmoud mahm...@arm.com>; Andrei Warkentin (awarken...@vmware.com)
> ; Jeremy Li
+ Ard’s new e-mail address
> -Original Message-
> From: Pete Batard
> Sent: Thursday, April 8, 2021 5:48 AM
> To: Jeremy Linton ; devel@edk2.groups.io
> Cc: Ard Biesheuvel ; l...@nuviainc.com; Samer
> El-Haj-Mahmoud ; Andrei Warkentin
> (awarken...@vmware.com)
> Subject: Re: [PATCH 2/3]
+ Ard's new e-mail address
From: Andrei Warkentin
Sent: Thursday, April 8, 2021 10:17 AM
To: Jeremy Linton ; devel@edk2.groups.io
Cc: Ard Biesheuvel ; l...@nuviainc.com; p...@akeo.ie;
Samer El-Haj-Mahmoud
Subject: Re: [PATCH 2/3] Platform/RaspberryPi/AcpiTables: Add further named
components
+Ard's new e-mail address
> -Original Message-
> From: Jeremy Linton
> Sent: Thursday, April 8, 2021 1:59 AM
> To: devel@edk2.groups.io
> Cc: Ard Biesheuvel ; l...@nuviainc.com;
> p...@akeo.ie; Samer El-Haj-Mahmoud mahm...@arm.com>; Andrei Warkentin (awarken...@vmware.com)
> ; Jeremy Lin
+Ard's new e-mail address
> -Original Message-
> From: Pete Batard
> Sent: Thursday, April 8, 2021 5:48 AM
> To: Jeremy Linton ; devel@edk2.groups.io
> Cc: Ard Biesheuvel ; l...@nuviainc.com; Samer
> El-Haj-Mahmoud ; Andrei Warkentin
> (awarken...@vmware.com)
> Subject: Re: [PATCH 3/3] P
+ Ard's new e-mail address
From: Samer El-Haj-Mahmoud
Sent: Friday, April 30, 2021 2:05 PM
To: devel@edk2.groups.io; Samer El-Haj-Mahmoud ;
Andrei Warkentin (awarken...@vmware.com) ; Jeremy Linton
Cc: Ard Biesheuvel ; l...@nuviainc.com; p...@akeo.ie;
Samer El-Haj-Mahmoud
Subject: RE: [edk2-
+Ard's new e-mail address
> -Original Message-
> From: Jeremy Linton
> Sent: Thursday, April 15, 2021 3:22 PM
> To: devel@edk2.groups.io
> Cc: Ard Biesheuvel ; l...@nuviainc.com;
> p...@akeo.ie; Samer El-Haj-Mahmoud mahm...@arm.com>; Andrei Warkentin (awarken...@vmware.com)
> ; Jeremy Li
+Ard's new e-mail address
> -Original Message-
> From: Jeremy Linton
> Sent: Thursday, April 15, 2021 3:22 PM
> To: devel@edk2.groups.io
> Cc: Ard Biesheuvel ; l...@nuviainc.com;
> p...@akeo.ie; Samer El-Haj-Mahmoud mahm...@arm.com>; Andrei Warkentin (awarken...@vmware.com)
> ; Jeremy Li
+Ard's new e-mail address
Jared, please confirm this is a "Reviewed-By"
> -Original Message-
> From: Jared McNeill
> Sent: Friday, April 30, 2021 6:30 AM
> To: Jeremy Linton
> Cc: devel@edk2.groups.io; Ard Biesheuvel ;
> l...@nuviainc.com; Pete Batard ; Samer El-Haj-Mahmoud
> ; Andrei W
+Ard's new e-mail address
Jared, I assume your response can be taken as a "Reviewed-By", correct?
> -Original Message-
> From: Jared McNeill
> Sent: Friday, April 30, 2021 9:08 PM
> To: Samer El-Haj-Mahmoud
> Cc: Jeremy Linton ; devel@edk2.groups.io; Ard
> Biesheuvel ; l...@nuviainc.com
+Ard's new e-mail address
> -Original Message-
> From: Jeremy Linton
> Sent: Thursday, April 15, 2021 3:22 PM
> To: devel@edk2.groups.io
> Cc: Ard Biesheuvel ; l...@nuviainc.com;
> p...@akeo.ie; Samer El-Haj-Mahmoud mahm...@arm.com>; Andrei Warkentin (awarken...@vmware.com)
> ; Jeremy Li
On Thu, 15 Apr 2021 at 21:22, Jeremy Linton wrote:
>
> Under normal circumstances GenetSimpleNetworkTransmit won't be
> called unless the rest of the network stack detects the link is
> up. So, during normal operation when the adapter is initialized
> the link naturally transitions to link up, and
On Thu, 15 Apr 2021 at 21:22, Jeremy Linton wrote:
>
> The genet is capable of addressing the entire memory space
> on the RPI4. Lets allow it to dma into those regions.
> This solves intermittent issues with grub/etc being able
> to communicate when the 3G limit is lifted on 8G boards.
>
> Signed
Hi,
On 5/10/21 11:56 AM, Ard Biesheuvel wrote:
On Thu, 15 Apr 2021 at 21:22, Jeremy Linton wrote:
Under normal circumstances GenetSimpleNetworkTransmit won't be
called unless the rest of the network stack detects the link is
up. So, during normal operation when the adapter is initialized
the
On Mon, 10 May 2021 at 19:26, Jeremy Linton wrote:
>
> Hi,
>
> On 5/10/21 11:56 AM, Ard Biesheuvel wrote:
> > On Thu, 15 Apr 2021 at 21:22, Jeremy Linton wrote:
> >>
> >> Under normal circumstances GenetSimpleNetworkTransmit won't be
> >> called unless the rest of the network stack detects the li
On Mon, May 10, 2021 at 05:57:08PM +0200, Ard Biesheuvel wrote:
> On Mon, 10 May 2021 at 09:53, Etienne Carriere
> wrote:
> >
> > This series brings support for building PlatformStandaloneMmRpmb for
> > 32bit Arm architectures. This series is based on series [1] in edk2
> > that allows to build St
On 5/10/21 9:24 AM, Lendacky, Thomas via groups.io wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3385
>
> A VS2012 build fails with a cast conversion warning when the SEV-ES work
> area PCD is cast as a pointer to the SEV_ES_AP_JMP_FAR type.
>
> When casting from a PCD value to a po
I forgot to say, this fixes
https://bugzilla.tianocore.org/show_bug.cgi?id=3116 .
--
Rebecca Cran
On 5/9/21 1:18 PM, Rebecca Cran wrote:
The existing instructions no longer work on macOS Big Sur and Xcode 12.5.
Update them to include for example using lldb instead of gdb, installing
XQuartz, a
I'm checking out the PREBUILD and POSTBUILD option in a DSC. I can launch my
scripts, etc.
When there is a POSTBUILD error, build.py properly says the build failed, but
build.py is still returning 0 (success). MyBuild.LaunchPostBuild() execution
does not look like it affects ReturnCode which
Changes since V2:
- Introduced CPU container object into DSDT
- Addressed comments from Sami
Changes since V1:
- Rebase the patches on top of latest master branch
- Addressed comments from Pierre
Processor Properties Topology Table (PPTT) describes the topological
structure of processors, and the
Add helper macros for the creation for PPTT table. These macros help
with initializing processor hierarchy node structure, cache type
structure and ID structure.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 170
1 file changed, 170 insertions
The SGI-575 platform includes two clusters with four single-thread CPUs.
Add processor container devices for the two clusters on the SGI-575
platform and move the existing processor devices into respective
processor containers.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/Sgi57
The RD-N1-Edge platform includes two clusters with four single-thread
CPUs. Add processor container devices for the two clusters on the
RD-N1-Edge platform and move the existing processor devices into
respective processor containers.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables
The SGI-575 platform includes two clusters with four single-thread CPUs.
Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache
and 512KB L2 cache. Each cluster includes a 2MB L3 cache. Add PPTT table
for SGI-575 platform with this information.
Signed-off-by: Pranav Madhu
---
Pla
The RD-N1-Edge dual-chip platform is composed of two RD-N1-Edge
platforms connected over a coherent link. Each chip has two clusters
with four CPUs in each cluster. Add the Differentiated System
Description Table (DSDT) ACPI table for this platform with processor
container devices defined containin
The RD-N1-Edge platform includes two clusters with four single-thread
CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction
cache and 512KB L2 cache. Each cluster includes a 2MB L3 cache. The
platform also includes a system level cache of 8MB. Add PPTT table for
RD-N1-Edge platform
The RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip
platforms connected over cache coherent interconnect. Each of the
RD-N1-Edge single-chip platform includes two clusters with four
single-thread CPUs. Each of the CPUs include 64KB L1 Data cache, 64KB
L1 Instruction cache and 512K
The RD-E1-Edge platform includes two clusters with eight multi-thread
CPUs. Each of the CPUs include 32KB L1 Data cache, 32KB L1 Instruction
cache and 256KB L2 cache. Each cluster includes a 2MB L3 cache. The
platform also includes a system level cache of 8MB. Add PPTT table for
RD-E1-Edge platform
The RD-V1 platform is a sixteen core platform with each core contained
in a minimal cluster logic. Update the processor device entries
accordingly in the DSDT ACPI table by moving each of the processor
device entries into a separate processor container device.
Signed-off-by: Pranav Madhu
---
Pla
The RD-V1 platform includes sixteen single-thread CPUs. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB
L2 cache. The platform also includes a system level cache of 16MB.
Add PPTT table for RD-V1 platform with this information.
Signed-off-by: Pranav Madhu
---
Platf
The RD-N2 platform is a sixteen core platform with each core contained
in a minimal cluster logic. Update the processor device entries
accordingly in the DSDT ACPI table by moving each of the processor
device entries into a separate processor container devices.
Signed-off-by: Pranav Madhu
---
Pl
The RD-V1 quad-chip platform is composed of four RD-V1 platforms
connected over a coherent link. Each chip has four CPU cores with each
core contained in a minimal cluster logic. Update the processor device
entries accordingly in the DSDT ACPI table by moving each of the
processor device entries in
The RD-V1 quad-chip platform consists of four chips connected over cache
coherent interconnect. Each chip on the platform includes four single-
thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1
Instruction cache and 1MB L2 cache. The platform also includes a system
level cache of 16
The RD-N2 platform includes sixteen single-thread CPUS. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2
cache. The platform also includes a system level cache of 32MB. Add PPTT
table for RD-N2 platform with this information.
Signed-off-by: Pranav Madhu
---
Platf
Update MdePkg BaseRngLib and SecurityPkg RngDxe to add support for
the AARCH64 RNDR instruction.
Changes from v2 to v3:
o Fixed the default value of
gEfiSecurityPkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm
to be an empty GUID.
o Removed RNDRRS since it wasn't being used.
o Fixed the commit me
Make BaseRngLib more generic by moving x86-specific functionality into
'Rand' and adding files under 'AArch64' to support the optional ARMv8.5
RNG instruction RNDR that is a part of FEAT_RNG.
Signed-off-by: Rebecca Cran
---
MdePkg/MdePkg.dec| 9 +-
MdePkg/Md
AARCH64 support has been added to BaseRngLib via the optional
ARMv8.5 FEAT_RNG.
Refactor RngDxe to support AARCH64, note support for it in the
VALID_ARCHITECTURES line of RngDxe.inf and enable it in SecurityPkg.dsc.
Signed-off-by: Rebecca Cran
---
SecurityPkg/SecurityPkg.dec
I think there a few categories of tool chains:
1) Tool chains that are in tools_def.txt and are used by EDK II CI to perform
pre-commit and post-commit changes. These are documented in Readme.rst
2) Tool chains that are in tools_def.txt that are fully supported by the EDK II
community. Should
Thanks. The obvious toolchains that are missing from ReadMe.rst are any
versions of XCODE and CLANG.
Also, it might be nice to specify _which_ GCC5 versions are supported,
since that covers gcc 5 through 11 and gcc 5.x currently causes a build
error. We maybe only care about gcc 7 and newer thes
> -Original Message-
> From: Liu, Zhiguang
> Sent: Monday, May 10, 2021 5:00 PM
> To: Wu, Hao A ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Gao, Zhichao
> ; Ni, Ray
> Subject: RE: [edk2-devel] [PATCH] MdeModulePkg: Retrive boot manager menu
> from any fv
>
> Hi Hao,
>
> I don't have the
Hao, I agree with you on the performance evaluation and function header update.
Besides that, I don't have other comments.
> -Original Message-
> From: Wu, Hao A
> Sent: Tuesday, May 11, 2021 9:20 AM
> To: Liu, Zhiguang ; Gao, Zhichao
> ; Ni, Ray ;
> devel@edk2.groups.io
> Cc: Wang, Jian
*Reminder:* TianoCore Bug Triage - APAC / NAMO
*When:* Tuesday, 11 May 2021, 6:30pm to 7:30pm, (GMT-07:00) America/Los Angeles
*Where:*
https://teams.microsoft.com/l/meetup-join/19%3ameeting_ZjQ3OTViZGUtYTM5ZS00MDBmLWFkNDYtYTg1ZTA1YTFhY2U3%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4e
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3384
Currently, UefiBootManagerLib has the below assumption:
Assume the BootManagerMenuFile is in the same FV as the module links to this
library.
It has some limitation now, so remove the assumption.
Cc: Jian J Wang
Cc: Hao A Wu
Cc: Zhicha
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3384
Currently, UefiBootManagerLib has the below assumption:
Assume the BootManagerMenuFile is in the same FV as the module links to this
library.
It has some limitation now, so remove the assumption.
Cc: Jian J Wang
Cc: Hao A Wu
Cc: Zhicha
Garrett:
I agree build should return error code reported from post build fail.
Seemly, current logic doesn’t handle the failure case.
Thanks
Liming
发件人: devel@edk2.groups.io 代表 Kirkendall, Garrett
发送时间: 2021年5月11日 4:05
收件人: devel@edk2.groups.io
主题: [edk2-devel] DSC POSTBUILD problem/questi
Thanks for your update. This version patches are good to me.
Reviewed-by: Liming Gao
> -邮件原件-
> 发件人: Rebecca Cran
> 发送时间: 2021年5月11日 5:53
> 收件人: devel@edk2.groups.io; Jiewen Yao ; Jian J
> Wang ; Michael D Kinney
> ; Liming Gao ;
> Zhiguang Liu ; Ard Biesheuvel
> ; Sami Mujawar
> 抄送:
Reviewed-by: Liming Gao
> -邮件原件-
> 发件人: devel@edk2.groups.io 代表 Lendacky,
> Thomas
> 发送时间: 2021年5月10日 22:25
> 收件人: devel@edk2.groups.io
> 抄送: Brijesh Singh ; Eric Dong
> ; Ray Ni ; Laszlo Ersek
> ; Rahul Kumar
> 主题: [edk2-devel] [PATCH] UefiCpuPkg/MpInitLib: Properly cast from PCD to
>
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