ect: [edk2-devel] question about cxl device enumeration in pci bus driver
Hi,
I have a question about cxl memory device hot-plug.
For example:
1. When cold boot, the platform has only 512GB cxl type-3 memory
2. During OS runtime, user hot-plug another cxl type-3 memory device expanding
to 1TB.
:* jonathan.came...@huawei.com, Laszlo Ersek ,
kra...@redhat.com, Ni, Ray , Sayanta Pattanayak
*Subject:* [edk2-devel] question about cxl device enumeration in pci bus
driver
Hi,
I have a question about cxl memory device hot-plug.
For example:
1. When cold boot, the platform has only 512GB cxl type-3
Hi,
I have a question about cxl memory device hot-plug.
For example:
1. When cold boot, the platform has only 512GB cxl type-3 memory
2. During OS runtime, user hot-plug another cxl type-3 memory device expanding
to 1TB.
So, how did OS identify another 512GB space newly added without a reboot
; Sayanta Pattanayak
Subject: Re:Re: [edk2-devel] question about cxl device enumeration in pci bus
driver
Hi,
Thanks for reply!
I download code from this git https://github.com/SayantaP-arm/edk2-platforms/
For this ARM edk2 sample package, it provided cxldxe driver which being
executed after UEFI
Hi,
Thanks for reply!
I download code from this git https://github.com/SayantaP-arm/edk2-platforms/
For this ARM edk2 sample package, it provided cxldxe driver which being
executed after UEFI DXE PciBus enumeration finishes.
This ppt (https://lpc.events/event/16/contributions/1254/) describ
Hi,
Thanks for reply!
I download code from this git https://github.com/SayantaP-arm/edk2-platforms/
For this ARM edk2 sample package, it provided cxldxe driver which being
executed after UEFI DXE PciBus enumeration finishes.
This ppt (https://lpc.events/event/16/contributions/1254/) describes
On Thu, 26 Oct 2023 11:49:28 +0200
"Laszlo Ersek" wrote:
> On 10/26/23 10:33, Gerd Hoffmann wrote:
> > On Thu, Oct 26, 2023 at 10:36:35AM +0800, Yoshinoya wrote:
> >
> >> CXL Host Bridge / Root Port / Switch / Device enumeration / HDM Config,
> >> maybe could be integrated into pci drivers st
On 10/26/23 10:33, Gerd Hoffmann wrote:
> On Thu, Oct 26, 2023 at 10:36:35AM +0800, Yoshinoya wrote:
>
>> CXL Host Bridge / Root Port / Switch / Device enumeration / HDM Config,
>> maybe could be integrated into pci drivers stack.
>
> Point being? Can or should the firmware do anything useful w
On Thu, Oct 26, 2023 at 10:36:35AM +0800, Yoshinoya wrote:
> CXL Host Bridge / Root Port / Switch / Device enumeration / HDM Config, maybe
> could be integrated into pci drivers stack.
Point being? Can or should the firmware do anything useful with
the CXL hardware? If so, what exactly and why
today's pci bus
driver.
But I might be wrong. Can you list any missing logic in pci bus driver?
Thanks,
Ray
From: devel@edk2.groups.io on behalf of Yoshinoya
Sent: Wednesday, October 25, 2023 2:01 PM
To: devel@edk2.groups.io
Subject: [edk2-devel] question about cxl device enumeration in pci
2023 2:01 PM
To: devel@edk2.groups.io
Subject: [edk2-devel] question about cxl device enumeration in pci bus driver
Hi,
CXL devices are more polular.
Is there any plan to add cxl device enumeration in pci bus driver?
Thanks
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages se
Hi,
CXL devices are more polular.
Is there any plan to add cxl device enumeration in pci bus driver?
Thanks
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#110016): https://edk2.groups.io/g/devel/message/110016
Mute This Topic: https://gr
12 matches
Mail list logo
