Thanks ray, below are really great feedback. I have checked all and response as
below:
> The default SMBASE for the x86 processor is 0x3. When SMI happens,
> CPU runs the
> SMI handler at SMBASE+0x8000. Also, the SMM save state area is within
> SMBASE+0x1.
>
> One of the SMM initializati
Jiaxin,
I know that you will submit v3 patch set to address Laszlo's comments.
Let me put my review comments on code logic here so you could take them into
account also.
1. I suggest we describe the HOB structure in this header file in file header
comments.
For example:
The default SMBASE for
> Subject: RE: [edk2-devel] [PATCH v2] UefiCpuPkg: Support SMM Relocated
> SmBase handling
>
> > >> v1:
> > >> - Thread: https://edk2.groups.io/g/devel/message/97748
> > >>
> > >> Change-Id: Iec7bf25166bfeefb44a202285465a35b5debbce4
> > >
> >> v1:
> >> - Thread: https://edk2.groups.io/g/devel/message/97748
> >>
> >> Change-Id: Iec7bf25166bfeefb44a202285465a35b5debbce4
> >
> > (1) Please don't include this in upstream patches.
> >
I will resubmit the series patches according your below comments.
> >> Cc: Eric Dong
> >> Cc: Ray Ni
On 1/12/23 13:37, Laszlo Ersek wrote:
> On 1/11/23 09:35, Wu, Jiaxin wrote:
>> Mainly changes as below:
>> 1. Add Smm Base HOB, which is used to store the information of
>> Smm Relocated SmBase array for each Processors;
>> 2. Combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate) into one
>> (g
On 1/11/23 09:35, Wu, Jiaxin wrote:
> Mainly changes as below:
> 1. Add Smm Base HOB, which is used to store the information of
> Smm Relocated SmBase array for each Processors;
> 2. Combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate) into one
> (gcSmiHandlerTemplate), the new SMI handler nee
Mainly changes as below:
1. Add Smm Base HOB, which is used to store the information of
Smm Relocated SmBase array for each Processors;
2. Combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate) into one
(gcSmiHandlerTemplate), the new SMI handler needs to run to 2 paths: one
to SmmCpuFeaturesIni
