On Mon, 2 Dec 2019 at 15:08, Ard Biesheuvel wrote:
>
> On Mon, 2 Dec 2019 at 13:02, Leif Lindholm wrote:
> >
> > On Mon, Dec 02, 2019 at 10:58:45 +0100, Ard Biesheuvel wrote:
> > > On Fri, 29 Nov 2019 at 13:13, Ard Biesheuvel
> > > wrote:
> > > >
> > > > On Fri, 29 Nov 2019 at 12:29, Leif Lindh
On Mon, 2 Dec 2019 at 13:02, Leif Lindholm wrote:
>
> On Mon, Dec 02, 2019 at 10:58:45 +0100, Ard Biesheuvel wrote:
> > On Fri, 29 Nov 2019 at 13:13, Ard Biesheuvel
> > wrote:
> > >
> > > On Fri, 29 Nov 2019 at 12:29, Leif Lindholm
> > > wrote:
> > > >
> > > > On Fri, Nov 29, 2019 at 11:47:14
On Mon, Dec 02, 2019 at 10:58:45 +0100, Ard Biesheuvel wrote:
> On Fri, 29 Nov 2019 at 13:13, Ard Biesheuvel
> wrote:
> >
> > On Fri, 29 Nov 2019 at 12:29, Leif Lindholm
> > wrote:
> > >
> > > On Fri, Nov 29, 2019 at 11:47:14 +0100, Ard Biesheuvel wrote:
> > > > Refactor the platform DXE a bit
On Fri, 29 Nov 2019 at 13:13, Ard Biesheuvel wrote:
>
> On Fri, 29 Nov 2019 at 12:29, Leif Lindholm wrote:
> >
> > On Fri, Nov 29, 2019 at 11:47:14 +0100, Ard Biesheuvel wrote:
> > > Refactor the platform DXE a bit in patch #1 so we can seamlessly drop in
> > > the code in patch #2 to expose a SS
On Fri, 29 Nov 2019 at 12:29, Leif Lindholm wrote:
>
> On Fri, Nov 29, 2019 at 11:47:14 +0100, Ard Biesheuvel wrote:
> > Refactor the platform DXE a bit in patch #1 so we can seamlessly drop in
> > the code in patch #2 to expose a SSDT with a device node describing
> > OP-TEE when booting in ACPI
On Fri, Nov 29, 2019 at 11:47:14 +0100, Ard Biesheuvel wrote:
> Refactor the platform DXE a bit in patch #1 so we can seamlessly drop in
> the code in patch #2 to expose a SSDT with a device node describing
> OP-TEE when booting in ACPI mode and OP-TEE is present.
If we need any more SSDTs for thi
Refactor the platform DXE a bit in patch #1 so we can seamlessly drop in
the code in patch #2 to expose a SSDT with a device node describing
OP-TEE when booting in ACPI mode and OP-TEE is present.
Ard Biesheuvel (2):
Silicon/SynQuacer/PlatformDxe: move EMMC SSDT handling to core routine
Silico