Reviewed-by: Min Xu
> -Original Message-
> From: Sun, CepingX
> Sent: Tuesday, February 27, 2024 5:19 AM
> To: devel@edk2.groups.io
> Cc: Sun, CepingX ; Aktas, Erdem
> ; James Bottomley ; Yao,
> Jiewen ; Xu, Min M ; Tom
> Lendacky ; Michael Roth
> ; Gerd Hoffmann ;
> Yamahata, Isaku
> S
On Tuesday, February 27, 2024 8:26 PM Yamahata, Isaku wrote:
> > +%macro tdcall_regs_preamble 2
> > +mov rax, %1
> > +
> > +xor rcx, rcx
> > +mov ecx, %2
> > +
> > +; R10 = 0 (standard TDVMCALL)
> > +
> > +xor r10d, r10d
> > +
> > +; Zero out unused (for standard TDVMCALL) r
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4696
>
> Refer to the [GHCI] spec, TDVF should clear the BIT5 for RBP in the mask.
> And TDVF should clear the regitsers to avoid leaking secrets to VMM.
>
> Reference:
> [GHCI]: TDX Guest-Host-Communication Interface v1.5
> https://cdrdv2.int
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4696
Refer to the [GHCI] spec, TDVF should clear the BIT5 for RBP in the mask.
And TDVF should clear the regitsers to avoid leaking secrets to VMM.
Reference:
[GHCI]: TDX Guest-Host-Communication Interface v1.5
https://cdrdv2.intel.com/v1/dl/get
