> Am 11.07.2019 um 19:07 schrieb Laszlo Ersek :
>
>> On 07/10/19 19:13, Leif Lindholm wrote:
>>> On Wed, Jul 10, 2019 at 04:53:11PM +0200, Alexander Graf via Groups.Io
>>> wrote:
>>> The PL031 interrupt mask register (IMSC) is not very clearly documented
>>> in the PL031 specification. However
On 07/10/19 19:13, Leif Lindholm wrote:
> On Wed, Jul 10, 2019 at 04:53:11PM +0200, Alexander Graf via Groups.Io wrote:
>> The PL031 interrupt mask register (IMSC) is not very clearly documented
>> in the PL031 specification. However, bit 0 (RTCIMSC) indicates whether
>> interrupts are enabled, not
On Wed, Jul 10, 2019 at 04:53:11PM +0200, Alexander Graf via Groups.Io wrote:
> The PL031 interrupt mask register (IMSC) is not very clearly documented
> in the PL031 specification. However, bit 0 (RTCIMSC) indicates whether
> interrupts are enabled, not disabled.
3.3.5. Interrupt Mask Set or Clea
The PL031 interrupt mask register (IMSC) is not very clearly documented
in the PL031 specification. However, bit 0 (RTCIMSC) indicates whether
interrupts are enabled, not disabled.
So before this commit, we were actually *enabling* interrupts for the RTC.
This patch changes the logic to instead d
