Hi Sami,
Thank you for reviewing the patch.
You are right. The do-while loop is redundant and hence can be removed.
Thanks,
Sahil
From: Sami Mujawar
Date: Wednesday, 29 May 2024 at 5:06 PM
To: Sahil Kaushal , devel@edk2.groups.io
Cc: Ard Biesheuvel , Leif Lindholm
, nd
Subject: Re: [edk2
From: sahil
This driver enables Fault Tolerant Write protocol, which provides
fault tolerant write capability for block devices.
Signed-off-by: sahil
---
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 5 +
Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 1 +
2 files changed, 6 insertions(+)
diff --git a
From: sahil
Enable persistent storage on QSPI flash device.
Signed-off-by: sahil
---
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 19 ++-
Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 2 ++
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/Platform/ARM/N1Sdp
From: sahil
In N1Sdp platform, the SoC is connected to IOFPGA which has a
Cadence Quad SPI (QSPI) controller. This QSPI controller manages
the flash chip device via QSPI bus.
This patch adds CadenceQspiNorFlashDeviceLib which is used to
manage and access the above configuration.
Signed-off-by
From: sahil
Add NOR flash library, this library provides APIs for getting the list
of NOR flash devices on the platform.
This flash is shared between AP core and System Control Processor. The
lower addresses are used to store SCP and AP boot images and higher
addresses will be used for variable
From: sahil
Enable SCP QSPI flash region access by adding it in the PlatformLibMem.
This flash is shared between AP core and System Control Processor. The
lower addresses are used to store SCP and AP boot images and higher
addresses will be used for variable storage.
Signed-off-by: sahil
From: sahil
This patch adds an optional functionality in NorFlashDxe to fetch and
print NOR Flash information from NorFlashInfoLib using its JEDEC ID.
NOR Flash libraries will implement a function "NorFlashReadID" which
will fetch and return JEDEC ID. This JEDEC ID can be then pri
From: sahil
This patch adds error_handler1 and error_handler2 labels in
NorFlashCreateInstance() function to handle the cleanup.
error_handler1: Frees just the Instance structure as the
ShadowBuffer is not allocated yet.
error_handler2: Frees both Instance and Instance->ShadowBuffer.
Sig
From: sahil
This variable holds the QSPI controller's base address.
It is defined in ARM.dec as well with the default value of 0x0.
In case a platform is not using it, they can just ignore this
variable and the default value of 0x0 will be propogated and
the variable will not be used.
S
From: sahil
NorFlashDeviceLib can be used to provide implementations of different
NOR Flash to NorFlashDxe, i.e. NorFlashDxe links with NorFlashDeviceLib
and the platforms can specify their respective NorFlashDeviceLib
instances.
This patch adds the following major changes:
1. Adds changes in
From: sahil
This patch implements functions to interact with P30 NOR Flash.
The code is taken from Platform/ARM/Drivers/NorFlashDxe/NorFlash.c
file.
Signed-off-by: sahil
---
Platform/ARM/Library/P30NorFlashDeviceLib/P30NorFlashDeviceLib.inf | 35 +
Platform/ARM/Library/P30NorFlashDeviceLib
From: sahil
NorFlashDeviceLib can be used to provide implementations of different
NOR Flash to NorFlashDxe, i.e. NorFlashDxe links with NorFlashDeviceLib
and the platforms can specify their respective NorFlashDeviceLib
instances.
This patch splits NorFlash.h and moves out the function
From: sahil
This patch makes local functions not being used outside
NorFlash.c STATIC.
Also, NorFlashWriteBuffer() is specific to a particular
flash implementation and need not be implemented by
other NOR flash device IPs.
Signed-off-by: sahil
---
Platform/ARM/Drivers/NorFlashDxe/NorFlash.h
From: sahil
This patch removes NorFlashReadCfiData() and NorFlashWrite()
prototypes from NorFlash.h as these are not implemented or
used anywhere in NorFlashDxe driver.
Signed-off-by: sahil
---
Platform/ARM/Drivers/NorFlashDxe/NorFlash.h | 17 -
1 file changed, 17 deletions
From: sahil
Refactoring done in this patch has two major parts:
1. Moving out NorFlashUnlockAndEraseSingleBlock and
NorFlashWriteFullBlock functions from NorFlashDxe.c and
NorFlashStandaloneMm.c to NorFlash.c files.
2. At the same time, we are adding NorFlashLock and NorFlashUnlock
functions
From: sahil
This patch splits NorFlash.h and adds NorFlashCommon.h which
will have all the flash independent functions and macros.
Whereas all the flash specific functions will be in NorFlash.h
header file.
Signed-off-by: sahil
---
Platform/ARM/Drivers/NorFlashDxe/NorFlashDxe.inf
From: sahil
Moving this function from NorFlash.c to NorFlashDxe.c as it is not
dependent on any particular flash implementation.
Signed-off-by: sahil
---
Platform/ARM/Drivers/NorFlashDxe/NorFlash.h| 14 +++
Platform/ARM/Drivers/NorFlashDxe/NorFlash.c| 44
From: sahil
Moving these functions from NorFlash.c to NorFlashBlockIoDxe.c as
they are not dependent on any particular flash implementation.
Signed-off-by: sahil
---
Platform/ARM/Drivers/NorFlashDxe/NorFlash.c | 129
Platform/ARM/Drivers/NorFlashDxe
From: sahil
This patch series adds the following changes:
1. Splits the NorFlashDxe driver to introduce a NorFlashDeviceLib that
implements the specifics for the respective flash. This will allow us
to plug different libraries implementing functionality of various NOR
Flash. The flash specific
From: sahil
This driver enables Fault Tolerant Write protocol, which provides
fault tolerant write capability for block devices.
Signed-off-by: sahil
---
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 5 +
Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 1 +
2 files changed, 6 insertions(+)
diff --git a
From: sahil
Enable persistent storage on QSPI flash device.
Signed-off-by: sahil
---
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 19 ++-
Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 2 ++
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/Platform/ARM/N1Sdp
From: sahil
In N1Sdp platform, the SoC is connected to IOFPGA which has a
Cadence Quad SPI (QSPI) controller. This QSPI controller manages
the flash chip device via QSPI bus.
This patch adds CadenceQspiNorFlashDeviceLib which is used to
manage and access the above configuration.
Signed-off-by
From: sahil
Add NOR flash library, this library provides APIs for getting the list
of NOR flash devices on the platform.
This flash is shared between AP core and System Control Processor. The
lower addresses are used to store SCP and AP boot images and higher
addresses will be used for variable
From: sahil
Enable SCP QSPI flash region access by adding it in the PlatformLibMem.
This flash is shared between AP core and System Control Processor. The
lower addresses are used to store SCP and AP boot images and higher
addresses will be used for variable storage.
Signed-off-by: sahil
From: sahil
This patch adds an optional functionality in NorFlashDxe to fetch and
print NOR Flash information from NorFlashInfoLib using its JEDEC ID.
NOR Flash libraries will implement a function "NorFlashReadID" which
will fetch and return JEDEC ID. This JEDEC ID can be then pri
From: sahil
This patch adds error_handler1 and error_handler2 labels in
NorFlashCreateInstance() function to handle the cleanup.
error_handler1: Frees just the Instance structure as the
ShadowBuffer is not allocated yet.
error_handler2: Frees both Instance and Instance->ShadowBuffer.
Sig
From: sahil
This variable holds the QSPI controller's base address.
It is defined in ARM.dec as well with the default value of 0x0.
In case a platform is not using it, they can just ignore this
variable and the default value of 0x0 will be propogated and
the variable will not be used.
S
From: sahil
NorFlashDeviceLib can be used to provide implementations of different
NOR Flash to NorFlashDxe, i.e. NorFlashDxe links with NorFlashDeviceLib
and the platforms can specify their respective NorFlashDeviceLib
instances.
This patch adds the following major changes:
1. Adds changes in
From: sahil
This patch implements functions to interact with P30 NOR Flash.
The code is taken from Platform/ARM/Drivers/NorFlashDxe/NorFlash.c
file.
Signed-off-by: sahil
---
Platform/ARM/Library/P30NorFlashDeviceLib/P30NorFlashDeviceLib.inf | 35 +
Platform/ARM/Library/P30NorFlashDeviceLib
From: sahil
NorFlashDeviceLib can be used to provide implementations of different
NOR Flash to NorFlashDxe, i.e. NorFlashDxe links with NorFlashDeviceLib
and the platforms can specify their respective NorFlashDeviceLib
instances.
This patch splits NorFlash.h and moves out the function
From: sahil
This patch makes local functions not being used outside
NorFlash.c STATIC.
Also, NorFlashWriteBuffer() is specific to a particular
flash implementation and need not be implemented by
other NOR flash device IPs.
Signed-off-by: sahil
---
Platform/ARM/Drivers/NorFlashDxe/NorFlash.h
From: sahil
This patch removes NorFlashReadCfiData() and NorFlashWrite()
prototypes from NorFlash.h as these are not implemented or
used anywhere in NorFlashDxe driver.
Signed-off-by: sahil
---
Platform/ARM/Drivers/NorFlashDxe/NorFlash.h | 17 -
1 file changed, 17 deletions
From: sahil
Refactoring done in this patch has two major parts:
1. Moving out NorFlashUnlockAndEraseSingleBlock and
NorFlashWriteFullBlock functions from NorFlashDxe.c and
NorFlashStandaloneMm.c to NorFlash.c files.
2. At the same time, we are adding NorFlashLock and NorFlashUnlock
functions
From: sahil
This patch splits NorFlash.h and adds NorFlashCommon.h which
will have all the flash independent functions and macros.
Whereas all the flash specific functions will be in NorFlash.h
header file.
Signed-off-by: sahil
---
Platform/ARM/Drivers/NorFlashDxe/NorFlashDxe.inf
From: sahil
Moving this function from NorFlash.c to NorFlashDxe.c as it is not
dependent on any particular flash implementation.
Signed-off-by: sahil
---
Platform/ARM/Drivers/NorFlashDxe/NorFlash.h| 14 +++
Platform/ARM/Drivers/NorFlashDxe/NorFlash.c| 44
From: sahil
Moving these functions from NorFlash.c to NorFlashBlockIoDxe.c as
they are not dependent on any particular flash implementation.
Signed-off-by: sahil
---
Platform/ARM/Drivers/NorFlashDxe/NorFlash.c | 129
Platform/ARM/Drivers/NorFlashDxe
From: sahil
This patch series adds the following changes:
1. Splits the NorFlashDxe driver to introduce a NorFlashDeviceLib that
implements the specifics for the respective flash. This will allow us
to plug different libraries implementing functionality of various NOR
Flash. The flash specific
Hi Sami,
Thank you for reviewing the patches.
Please find my comments inline below marked as [SAHIL].
On Thu, 16 May 2024 at 20:54, Sami Mujawar via groups.io
wrote:
>
> Hi Sahil,
>
> Thank you for this patch.
>
> I have some suggestions marked inline below, otherwise this patc
Hi Sami,
Thank you for reviewing the patches.
Please find my comments inline below marked as [SAHIL].
Also, for the documentation headers, I will try to add in
NorFlashDeviceLib.h and keep it consistent with
CadenceQspiNorFlashDeviceLib.
On Thu, 16 May 2024 at 20:48, Sami Mujawar via groups.io
Hi Pierre, Thanks for reviewing the patchset. Please find my comment inline
below.
On Thu, 2 May 2024 at 18:47, PierreGondois via groups.io wrote:
>
> Hello Sahil,
>
> On 4/23/24 07:56, Sahil Kaushal via groups.io wrote:
> > From: sahil
> >
> > In N1Sdp platform,
From: sahil
In N1Sdp platform, the SoC is connected to IOFPGA which has a
Cadence Quad SPI (QSPI) controller. This QSPI controller manages
the flash chip device via QSPI bus.
This patch adds CadenceQspiNorFlashDeviceLib which is used to
manage and access the above configuration.
Signed-off-by
From: sahil
This driver enables Fault Tolerant Write protocol, which provides
fault tolerant write capability for block devices.
Signed-off-by: sahil
---
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 5 +
Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 1 +
2 files changed, 6 insertions(+)
diff --git a
From: sahil
Enable persistent storage on QSPI flash device.
Signed-off-by: sahil
---
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 19 ++-
Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 2 ++
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/Platform/ARM/N1Sdp
From: sahil
This patch adds an optional functionality in NorFlashDxe to fetch and
print NOR Flash information from NorFlashInfoLib using its JEDEC ID.
NOR Flash libraries will implement a function "NorFlashReadID" which
will fetch and return JEDEC ID. This JEDEC ID can be then used to
From: sahil
NorFlashDeviceLib can be used to provide implementations of different
NOR Flash to NorFlashDxe, i.e. NorFlashDxe links with NorFlashDeviceLib
and the platforms can specify their respective NorFlashDeviceLib
instances.
This patch adds the following major changes:
1. Adds changes in
From: sahil
NorFlashDeviceLib can be used to provide implementations of different
NOR Flash to NorFlashDxe, i.e. NorFlashDxe links with NorFlashDeviceLib
and the platforms can specify their respective NorFlashDeviceLib
instances.
This patch splits NorFlash.h and moves out the function
From: sahil
This variable holds the QSPI controller's base address.
It is defined in ARM.dec as well with the default value of 0x0.
In case a platform is not using it, they can just ignore this
variable and the default value of 0x0 will be propogated and
the variable will not be used.
S
From: sahil
Enable SCP QSPI flash region access by adding it in the PlatformLibMem.
This flash is shared between AP core and System Control Processor. The
lower addresses are used to store SCP and AP boot images and higher
addresses will be used for variable storage.
Signed-off-by: sahil
From: sahil
Refactoring done in this patch has two major parts:
1. Moving out NorFlashUnlockAndEraseSingleBlock and
NorFlashWriteFullBlock functions from NorFlashDxe.c and
NorFlashStandaloneMm.c to NorFlash.c files.
2. At the same time, we are adding NorFlashLock and NorFlashUnlock
functions
From: sahil
Add NOR flash library, this library provides APIs for getting the list
of NOR flash devices on the platform.
Signed-off-by: sahil
---
Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf | 34 ++
Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c | 65
From: sahil
Moving these functions from NorFlash.c to NorFlashBlockIoDxe.c as
they are not dependent on any particular flash implementation.
Signed-off-by: sahil
---
Platform/ARM/Drivers/NorFlashDxe/NorFlash.c | 129
Platform/ARM/Drivers/NorFlashDxe
From: sahil
This patch splits NorFlash.h and adds NorFlashCommon.h which
will have all the flash independent functions and macros.
Whereas all the flash specific functions will be in NorFlash.h
header file.
Signed-off-by: sahil
---
Platform/ARM/Drivers/NorFlashDxe/NorFlashDxe.inf
From: sahil
This patch implements functions to interact with P30 NOR Flash.
The code is taken from Platform/ARM/Drivers/NorFlashDxe/NorFlash.c
file.
Signed-off-by: sahil
---
Platform/ARM/Library/P30NorFlashDeviceLib/P30NorFlashDeviceLib.inf | 35 +
Platform/ARM/Library/P30NorFlashDeviceLib
From: sahil
Moving this function from NorFlash.c to NorFlashDxe.c as it is not
dependent on any particular flash implementation.
Signed-off-by: sahil
---
Platform/ARM/Drivers/NorFlashDxe/NorFlash.h| 14 +++
Platform/ARM/Drivers/NorFlashDxe/NorFlash.c| 44
From: sahil
This patch series adds the following changes:
1. Splits the NorFlashDxe driver to introduce a NorFlashDeviceLib that
implements the specifics for the respective flash. This will allow us
to plug different libraries implementing functionality of various NOR
Flash. The flash specific
Hi All,
Please find the links to previous discussions below :
V1 -
https://edk2.groups.io/g/devel/topic/96088980#100022
V2 -
https://edk2.groups.io/g/devel/topic/96671861#103652
V3 -
https://edk2.groups.io/g/devel/topic/100912169#112452
Thanks,
Sahil
On Thu, 4 Jan 2024 at 18:46, sahil wrote
Hi All,
Please find the links to previous discussions below :
V1 -
https://edk2.groups.io/g/devel/topic/96088980#100022
V2 -
https://edk2.groups.io/g/devel/topic/96671861#103652
V3 -
https://edk2.groups.io/g/devel/topic/100912169#112452
Thanks,
Sahil
On Thu, 4 Jan 2024 at 18:46, sahil wrote
Hi All,
Please find the links to previous discussions below :
V1 -
https://edk2.groups.io/g/devel/topic/96088980#100022
V2 -
https://edk2.groups.io/g/devel/topic/96671861#103652
V3 -
https://edk2.groups.io/g/devel/topic/100912169#112452
Thanks,
Sahil
On Thu, 4 Jan 2024 at 18:46, sahil wrote
Hi All,
Please find the links to previous discussions below :
V1 -
https://edk2.groups.io/g/devel/topic/96088980#100022
V2 -
https://edk2.groups.io/g/devel/topic/96671861#103652
V3 -
https://edk2.groups.io/g/devel/topic/100912169#112452
Thanks,
Sahil
On Thu, 4 Jan 2024 at 18:46, sahil wrote
platform information from a fixed address
is also removed in this patch.
Signed-off-by: sahil
---
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
| 6 +++-
Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
| 1
Incorporate N1SdpNtFwConfigPei PEI module which parses NT_FW_CONFIG and
passes it to other PEI modules(as PPI) and DXE modules(as HOB).
Signed-off-by: sahil
---
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 3 +++
Platform/ARM/N1Sdp/N1SdpPlatform.dsc| 5 -
Platform/ARM/N1Sdp
PEI modules(as PPI) and DXE modules(as HOB).
v4:
- Fixed code review comments
- Split the patch into four patches
sahil (4):
Silicon/ARM/NeoverseN1Soc: Extract NT_FW_CONFIG address passed by TF-A
Platform/ARM/N1Sdp: Add N1SdpNtFwConfigPei PEI module
Platform/ARM/N1Sdp: Enable
This patch adds a PEI to parse NT_FW_CONFIG and pass it to
other PEI modules(as PPI) and DXE modules(as HOB).
Signed-off-by: sahil
---
Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.inf | 41 ++
Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.c | 132
NT_FW_CONFIG DTB contains platform information passed by TF-A boot
stage. This patch enables support to first extract address of
NT_FW_CONFIG and then pass it to other modules as a PPI.
Signed-off-by: sahil
---
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec| 5 -
Silicon
Signed-off-by: sahil
---
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 5 +
Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 1 +
2 files changed, 6 insertions(+)
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
index 10fe2db9e1b1..703829bbac99 100644
--- a/Platform
Enable persistent storage on QSPI flash device.
Signed-off-by: sahil
---
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 20 ++--
Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 4 +++-
2 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
b
Add NOR flash DXE driver, this brings up NV storage on
QSPI's flash device using FVB protocol.
Signed-off-by: sahil
---
Platform/ARM/N1Sdp/N1SdpPlatform.dec |5 +-
Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf | 72 ++
Platform/ARM/N1Sdp/Dr
Add NOR flash library, this library provides APIs for getting the list
of NOR flash devices on the platform.
Signed-off-by: sahil
---
Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf | 36
++
Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c | 52
/edk2-platforms/tree/n1sdp_persistent_storage
sahil (5):
Silicon/ARM/NeoverseN1Soc: Enable SCP QSPI flash region
Silicon/ARM/NeoverseN1Soc: NOR flash library for N1Sdp
Platform/ARM/N1Sdp: NOR flash Dxe Driver for N1Sdp
Platform/ARM/N1Sdp: Persistent storage for N1Sdp
Platform/ARM/N1Sdp
Enable SCP QSPI flash region access by adding it in the PlatformLibMem
Signed-off-by: sahil
---
Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 6 +-
Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 10 --
2 files changed, 13 insertions(+), 3
On Wednesday, September 6, 2023 11:51:31 PM IST Pedro Falcato wrote:
> On Wed, Sep 6, 2023 at 7:14 PM Sahil wrote:
> > Hi,
> >
> > I have never contributed to Tianocore. While I am comfortable with C and
> > Python, I don't have much experience with firmware deve
.github.io/wiki/Tasks
[2]
https://github.com/tianocore/tianocore.github.io/wiki/Tasks#user-content-Network_Block_Device_NBD_client
[3]
https://github.com/tianocore/tianocore.github.io/wiki/Tasks-Network-Block-Device
Warm regards,
Sahil
Github: https://github.com/valdaarhun
-=-=-=-=-=-=-=-=-=
PEI modules(as PPI) and DXE modules(as HOB).
Signed-off-by: sahil
---
Notes:
v3:
- Fixed code review comments
- Added a PEI to parse nt_fw_config
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
| 8 +-
Platform/ARM/N1Sdp
RemoteDdrSize calculation wraps around when booting N1Sdp in
multichip mode. Casting it to UINT64 to fix the issue.
Signed-off-by: sahil
---
Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Silicon/ARM
RemoteDdrSize calculation wraps around when booting N1Sdp in
multichip mode. Casting it to UINT64 to fix the issue.
Signed-off-by: sahil
Change-Id: Ic51269a8d67669684a5f056701cfbef6beb23da2
---
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
| 2 +-
1
V2 delta changes:
Split the patch in two for Platform/ARM/N1Sdp and Silicon/ARM/NeoverseN1Soc
sahil (2):
Platform/ARM/N1Sdp: Fix RemoteDdrSize cast
Silicon/ARM/NeoverseN1Soc: Fix RemoteDdrSize cast
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
| 2
Hi Thomas/Sami,
This issue arose while fixing comments during upstreaming the
following patch - https://edk2.groups.io/g/devel/topic/83261392#76845
and was observed while we were testing the platform with upstream code.
Thanks,
Sahil
On Thu, 26 Jan 2023 at 00:48, Thomas Abraham wrote:
>
>
On Wed, 8 Feb 2023 at 10:52, Sahil wrote:
>
> Hi Thomas/Sami,
>
> This issue arose while fixing comments during upstreaming the
> following patch - https://edk2.groups.io/g/devel/topic/83261392#76845
> and was observed while we were testing the platform with upstream cod
Hi Thomas/Sami,
This issue arose while fixing comments during upstreaming the
following patch - https://edk2.groups.io/g/devel/topic/83261392#76845
and was observed while we were testing the platform with upstream code.
Thanks,
Sahil
On Thu, 26 Jan 2023 at 02:17, Thomas Abraham wrote:
>
&
NT_FW_CONFIG DTB contains platform information passed by
Tf-A boot stage.
This information is used for Virtual memory map generation
during PEI phase and passed on to DXE phase as a HOB, where
it is used in ConfigurationManagerDxe.
Signed-off-by: sahil
---
Notes:
v2:
- Fixed code review
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=4317
The "if" condition on line 554 ensures that Guid won't be NULL (or 0) on line
600.
So, there will never be a situation where the "else" block on line 603 is
executed.
Signed-off-by: Sahil Siddiq
---
MdeModule
NT_FW_CONFIG DTB contains platform information passed by
Tf-A boot stage.
This information is used for Virtual memory map generation
during PEI phase and passed on to DXE phase as a HOB, where
it is used in ConfigurationManagerDxe.
Signed-off-by: sahil
---
Silicon/ARM/NeoverseN1Soc
From: Himanshu Sharma
In DBG2 table, IRQ ID was set as 0 for the UART. This overwrote the
IPI0 trigger method to "level", which prevented SGI0 to be enabled
again after a CPU offline/online cycle.
This patch fixes the above issue by assigning a reserved IRQ ID
for the Debug UART, other than 0 an
RemoteDdrSize calculation wraps around when booting N1Sdp in
multichip mode. Casting it to UINT64 to fix the issue.
Signed-off-by: sahil
---
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
| 2 +-
Silicon/ARM/NeoverseN1Soc/Library/PlatformLib
ch.
2. CCIX protocol messages flow over regular PCIe.
3. CCIX devices and root ports are natively discovered using the CCIX DVSEC.
Therefore, reuse PCIe PNP ID for CCIX.
Signed-off-by: sahil
---
Notes:
v3:
- added more info regarding the change in commit message [Sami Mujawar]
There is no need for a separate ID for CCIX host bridge,
therefore reusing PCIe PNP ID for CCIX.
Signed-off-by: sahil
---
Notes:
v2:
- removed licence fix, to be pushed separately [Leif Lindholm]
Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c | 4 ++--
1 file
There is no need for a separate ID for CCIX host bridge,
therefore reusing PCIe PNP ID for CCIX.
Also, updating the file's license to resolve error during
ECC checks.
Signed-off-by: sahil
---
Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c | 17
+
1
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