On Thu, Dec 12, 2024 at 11:51:54AM +0800, Yuquan Wang wrote:
> On Wed, Dec 11, 2024 at 03:40:03PM +, Alejandro Lucero Palau wrote:
> >
> > On 12/10/24 10:36, Yuquan Wang wrote:
> > > v3 -> v4:
> > > - Align base addresses of CXL relevant Windows
> >
On Wed, Dec 11, 2024 at 03:40:03PM +, Alejandro Lucero Palau wrote:
>
> On 12/10/24 10:36, Yuquan Wang wrote:
> > v3 -> v4:
> > - Align base addresses of CXL relevant Windows
> >
> > v2 -> v3:
> > - PCDs values of pio, mmio32, mmio64 & ecam spa
This adds #defines and struct typedefs for the various structure
types in the CXL Early Discovery Table (CEDT).
Signed-off-by: Yuquan Wang
---
MdePkg/Include/IndustryStandard/Cxl20.h | 41 +
MdePkg/Include/IndustryStandard/Cxl30.h | 59 +
MdePkg/Include
ntroduced.
Yuquan Wang (1):
MdePkg/IndustryStandard: add definitions for CXL CEDT
MdePkg/Include/IndustryStandard/Cxl20.h | 41 +
MdePkg/Include/IndustryStandard/Cxl30.h | 59 +
MdePkg/Include/IndustryStandard/Cxl31.h | 47
3 files cha
To provide CFMWs on sbsa-ref, this extends 1TB space from the
hole above RAM Memory [SBSA_MEM] for CXL Fixed Memory Window.
Signed-off-by: Yuquan Wang
---
docs/system/arm/sbsa.rst | 4 ++
hw/arm/sbsa-ref.c | 122 +-
hw/cxl/cxl-host-stubs.c | 2 +
hw
awei.com/
[2]: https://edk2.groups.io/g/devel/topic/rfc_edk2_patch_v3_0_1/109403423#
[3]: https://edk2.groups.io/g/devel/topic/rfc_patch_edk2_platforms_v2/109403456
Yuquan Wang (1):
hw/arm/sbsa-ref: Support CXL Host Bridge & CFMW
docs/system/arm/sbsa.rst | 4 ++
hw/arm/sbsa-ref.c | 122 +
CXL Fixed Memory Window structure which
are implemented as two independent space on sbsa-ref:
[SBSA_CXL_HOST] & [SBSA_CXL_FIXED_WINDOW].
Signed-off-by: Yuquan Wang
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 23 +-
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 19 +
Silicon/Qemu/
QtgId : 0001
[068h 0104 004h]First Target : 0001
Link:
[1]:
https://lore.kernel.org/linux-cxl/20220616141950.23374-2-jonathan.came...@huawei.com/
[2]: https://edk2.groups.io/g/devel/topic/rfc_edk2_patch_v3_0_1/109403423#
Yuquan Wang (1):
SbsaQemu: Support basic
CXL Fixed Memory Window structure which
are implemented as two independent space on sbsa-ref:
[SBSA_CXL_HOST] & [SBSA_CXL_FIXED_WINDOW].
Signed-off-by: Yuquan Wang
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 23 +-
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 19 +
Silicon/Qemu/
e on sbsa-ref.
Link:
[1]:
https://lore.kernel.org/linux-cxl/20220616141950.23374-2-jonathan.came...@huawei.com/
[2]: https://edk2.groups.io/g/devel/topic/rfc_edk2_patch_v3_0_1/109403423#
Yuquan Wang (1):
SbsaQemu: Support basic CXL enablement
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 23
ing qemu-build-Acpi tables.
Thus I
introduce fundamental structures of CEDT into the header file for the spec they
were
introduced.
Yuquan Wang (1):
MdePkg/IndustryStandard: add definitions for CXL CEDT
MdePkg/Include/IndustryStandard/Cxl20.h | 38
MdePkg/Incl
This adds #defines and struct typedefs for the various structure
types in the CXL Early Discovery Table (CEDT).
Signed-off-by: Yuquan Wang
---
MdePkg/Include/IndustryStandard/Cxl20.h | 38
MdePkg/Include/IndustryStandard/Cxl30.h | 46 +
MdePkg
This adds #defines and struct typedefs for the various structure
types in the CXL3.1 CXL Early Discovery Table (CEDT).
Signed-off-by: Yuquan Wang
---
.../IndustryStandard/CxlEarlyDiscoveryTable.h | 113 ++
1 file changed, 113 insertions(+)
create mode 100644 MdePkg/Include
t cxl on Qemu sbsa-ref platform, but it relies on CXL ACPI
elements
within compiled UEFI flash instead of virt/i386 using qemu-build-Acpi tables.
Thus I
create the header file CxlEarlyDiscoveryTable.h as the fundamental format for
CEDT building
in edk2-platforms.
Yuquan Wang (1):
-off-by: Yuquan Wang
---
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 6 +-
Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc| 70 +++
Silicon/Qemu/SbsaQemu/SbsaQemu.dec| 7 ++
3 files changed, 82 insertions(+), 1 deletion(-)
create mode 100644 Silicon/Qemu/Sbsa
f the new space layout would bring a series of bad
influence, but it seems that the base address and size of cxl host
bridge is ok.
Signed-off-by: Yuquan Wang
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 30 +-
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 14 +
Silicon/Qemu/SbsaQemu/A
groups.io/g/devel/topic/rfc_patch_0_1/108173029
Yuquan Wang (2):
SbsaQemu: Add acpi0016 & acpi0017 objects into DSDT
SbsaQemu: AcpiTables: Add CEDT Table
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 30 +-
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 20 +-
Silicon/Qemu/Sb
This adds #defines and struct typedefs for the various structure
types in the ACPI 6.4 CXL Early Discovery Table (CEDT).
Signed-off-by: Yuquan Wang
---
MdePkg/Include/IndustryStandard/Acpi64.h | 5 ++
.../IndustryStandard/CXLEarlyDiscoveryTable.h | 69 +++
2 files changed
build-Acpi tables.
Thus I
create the header file CXLEarlyDiscoveryTable.h as the fundamental format for
CEDT building
in edk2-platforms.
Yuquan Wang (1):
MdePkg/IndustryStandard: add definitions for ACPI 6.4 CEDT
MdePkg/Include/IndustryStandard/Acpi64.h | 5 ++
.../IndustrySta
On 2023-12-08 15:42, Yoshinoya wrote:
There is a description about UEFI Drivers in 1.4 Abbreviations in this doc.
UEFI Drivers : UEFI CXL Bus and memory device drivers.
I think UEFI CXL Drivers is a part of System Firmware(UEFI BIOS).
These UEFI Drivers may do some basic configuation for some
Addition: [the link of CXL Memory Device SW Guide]
https://cdrdv2-public.intel.com/643805/643805_CXL%20Memory%20Device%20SW%20Guide_Rev1p0.pdf
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Hi, folks
CXL Memory Device SW Guide [1] rev1.0 2.4 provides little description about the
difference between System Firmware and
UEFI CXL drivers. IIRC, the UEFI drivers are part of system firmware, so I am
confused about the boundary on them.
I greatly appreciate insight/help in this regard!
for sbsa-ref.
Signed-off-by: Yuquan Wang
---
Silicon/Qemu/SbsaQemu/SbsaQemu.dec| 4 +-
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +--
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 4 +-
.../SbsaQemuPlatformDxe.inf | 2 +
.../SbsaQemuPlatformDxe
USB hierarchy in DSDT
- changed two usb ports from type A to type C
- refactored patchset
v1 -> v2:
- rebased on master as v1 did not applied
- moved pcd setting in dec file into the first commit
Yuquan Wang (1):
Platform/SbsaQemu: add XHCI support and replace EHCI
Silicon/Qemu/SbsaQemu/SbsaQe
On 2023-09-05 14:30, marcin.juszkiewicz wrote:
Project is meant to be buildable at every commit. Your patchset breaks
that rule.
Oh! I get it ! I did not consider this principle when designing these patches.
Thanks for your explanation : ) I am going to recheck and combine some content
toge
Hi, Leif
On 2023-09-04 21:51, quic_llindhol wrote:
>
> However, this version still breaks bisect: attempting to build at 1/3
> or 2/3 leads to:
> ---
> /work/git/edk2-platforms/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf(72):
> error 3000: PCD
> [gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlat
Hi, Leif
On 2023-08-31 21:06, Leif wrote:
I had to move one hunk (.dec change) from 2/3 to 1/3 in order to
not break bisect.
If you're happy with the slightly modified version, I think this
is good to go in. Please let me know.
It' ok.
In the second version of this series patches, in fact,
Define the pcd settings for identifying the base address of XHCI
and XHCI's mmio size, and remove relevant EHCI settings.
Signed-off-by: Yuquan Wang
---
Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 4 ++--
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +++---
2 files changed, 5 insertions(+), 5 dele
As sbsa-ref board uses xhci to replace ehci, the DSDT is updated to match
the platform xhci controller. This also removes previous ehci structure.
Signed-off-by: Yuquan Wang
---
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 4 +-
Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 125
This registers the non-discoverable XHCI for sbsa-ref.
Signed-off-by: Yuquan Wang
---
.../SbsaQemuPlatformDxe.inf | 2 +
.../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 41 +++
2 files changed, 34 insertions(+), 9 deletions(-)
diff --git
a/Silicon/Qemu
did not applied
- moved pcd setting in dec file into the first commit
Yuquan Wang (3):
Platform/Qemu/SbsaQemu/SbsaQemu.dsc: define XHCI Pcd settings
SbsaQemu: Drivers: Add initial support for XHCI
SbsaQemu: AcpiTables: Add XHCI info into DSDT
Silicon/Qemu/SbsaQemu/SbsaQemu.dec|
Hi, Marcin
On 2023-07-04 15:36, marcin.juszkiewicz wrote:
The problem is with QEMU 8.0.0 (no GIC ITS) where I get some kernel
complaints about interrupts. And this is what I am working on right now.
https://github.com/hrw/fork-edk2-platforms/commits/submit/0628-its has
my work-in-progress tre
Hi Marcin,
Sorry to disturb you but I would like to consult you a little question about
this patch because of my lack of engineering experience:
Q: It seems like that the third patch will delete Iort.aslc file and moving the
creation of IORT into SbsaQemuAcpiDxe driver, so the firmware can dyna
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