When build in DEBUG, the code asserts that 5LPage support is there
when the physical address width is larger than 48.
In a RELEASE build it will just force LA57 to 1 in CR4
even if CPUID(7).ECX[16] says it is not supported.
The hang (in the ASSERT) in DEBUG is not warranted as there are
legal conf
The DSDT had a syntax error that was not detected by older iasl versions.
This commit fixes the Syntax error.
Signed-off-by: Robert Guenzel
---
Platform/Intel/SimicsOpenBoardPkg/AcpiTables/Dsdt.asl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platform/Intel/SimicsOpenBoa
The Pcd gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable is by default True
in UefiCpuPkg.
However, the Simics target does not have the MSRs whose access is guarded by
this Pcd and
hence runs into a GP fault. Consequently, we override the Pcd to be False.
Signed-off-by: Robert Guenzel
---
