ing.
Best regards,
Benjamin
On December 10, 2024 9:38:28 p.m. EST, "Liu, Linus" wrote:
>Hi Benjamin
>May I know what the problem in coreboot is?
>
>Thanks
>
>
>From: Liu, Linus
>Sent: Tuesday, December 10, 2024 1:42 PM
>To: Benjamin Doron ; devel@edk2.groups.i
Hi,
In
https://github.com/tianocore/edk2/blob/a0ac7cf/UefiPayloadPkg/UefiPayloadEntry/FitUniversalPayloadEntry.c#L220,
UefiPayload parses its own UPL FIT's FDT to determine where the other FVs
can be found (if you follow the references backwards, you'll see that
gUniversalPayloadBaseGuid HOBs come
Hi all,
We're planning to refactor the shell into a library so that shell apps
possibly used in the field for testing can be easily adapted for automation.
Our plan is:
- Refactor ShellInfoObject into base internals and interactive elements
- Migrate functions that imply interactivity into
>Nate
>
>From: devel@edk2.groups.io on behalf of Benjamin Doron
>
>Date: Tuesday, January 9, 2024 at 3:48 PM
>To: Ma <>, Ma, Hua , devel@edk2.groups.io
>
>Subject: Re: [edk2-devel] [PATCH] UefiPayloadPkg: Add macro to enable
>selection of timer
>Hi,
>Are the
Hi,
Are there platforms that will use this? What advantages does using the LAPIC as
a timer offer? Thanks.
Regards,
Benjamin
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Mute This
From: Benjamin Doron
Former Intel platforms controlled SMRAM protection using a dedicated
register.
SlimBootloader-supported platforms have converged on the SMRR, but for
coreboot to support prior platforms too, lock-down is advised.
Requires testing.
TODO: It is more correct to install a
From: Benjamin Doron
To be used with the https://review.coreboot.org/c/coreboot/+/70378
patch-series. Now feature complete, awaiting final upstream feedback
whether generating some data inside coreboot is okay.
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by
From: Benjamin Doron
Parse coreboot FMAP structures to find the memory region in SPI flash
by the FMAP area name.
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: Benjamin Doron
---
UefiPayloadPkg/Include/Coreboot.h | 21
From: Benjamin Doron
UefiPayload does not install all SBL HOBs, EDK2-relevant ones must be
installed individually. This was omitted from the SMM feature pushes.
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: Benjamin Doron
---
UefiPayloadPkg/Library
From: Benjamin Doron
Former Intel platforms controlled SMRAM protection using a dedicated
register.
SlimBootloader-supported platforms have converged on the SMRR, but for
coreboot to support prior platforms too, lock-down is advised.
Requires testing.
TODO: It is more correct to install a
From: Benjamin Doron
To be used with the https://review.coreboot.org/c/coreboot/+/70378
patch-series. Now feature complete, awaiting final upstream feedback
whether generating some data inside coreboot is okay.
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by
From: Benjamin Doron
Parse coreboot FMAP structures to find the memory region in SPI flash
by the FMAP area name.
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: Benjamin Doron
---
UefiPayloadPkg/Include/Coreboot.h | 21
From: Benjamin Doron
UefiPayload does not install all SBL HOBs, EDK2-relevant ones must be
installed individually. This was omitted from the SMM feature pushes.
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: Benjamin Doron
---
UefiPayloadPkg/Library
Sure. Done, see https://github.com/tianocore/edk2/pull/4337.
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Group Owner: devel+ow.
e the platform builder may want behaviour or
information from the DEBUG_CODE macros. Therefore, separate this into
another build flag.
Bitwise ORs enable this flexibility.
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: Benjamin Doron
---
UefiPaylo
t library is also used in SEC and PEI phase, we will need
>another DXE library to avoid build error or possible system hang while the
>Boot Service is not available in PEI or SEC phase.
>
>From: Benjamin Doron
>Sent: Friday, April 28, 2023 1:36 AM
>To: Hsieh, PaytonX ;
Hi,
Can you deduplicate this code by moving the functions into a common, or "base"
file, and DXE's constructor and event into a separate file? As I see it, it
should be alright to reuse DXE's functions for other phases, the `
mBaseSerialPortLibHobAtRuntime` variable will never be changed in this
Hi,
Is there merit to removing the assert statement? When this instance of the
RngLib class is used, the platform builder says there's RNG support. Asserts
are a little easier to see than debug prints, especially when they stall the
platform. I think that leaving it in is better. If asserts don'
I hadn't seen the bugzilla yet, though I know the issue. See patch 1/2, the
current approach is to use RngLibTimerLib if the build-time configuration
indicates. This isn't recommended but sufficient for building for platforms
which require the library class - I think OpensslLib has a dependency.
Please see https://edk2.groups.io/g/devel/message/103583 and
https://edk2.groups.io/g/devel/message/103584. Thanks.
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Mute This Topic: ht
From: Benjamin Doron
Presently, `ArchIsRngSupported()` always returns TRUE, per
https://github.com/tianocore/edk2/blob/1eeca0750af5af2f0e78437bf791ac2de74bde74/MdePkg/Library/BaseRngLib/Rand/RdRand.c#L124-L125.
Therefore, `BaseRngLibConstructor()` should continue to assert RDRAND
support
From: Benjamin Doron
Uses CPU RDRAND support and installs the EfiRngProtocol.
The protocol may be used by iPXE or the Linux kernel to gather entropy.
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: Benjamin Doron
---
UefiPayloadPkg/UefiPayloadPkg.dsc | 3
Init/PlatformInitPei/PlatformInitPreMem.c#L164-L201
[2]:
https://github.com/tianocore/edk2/blob/edk2-stable202011/UefiPayloadPkg/BlSupportPei/BlSupportPei.c#L462-L466
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: Benjamin Doron
---
.../UefiPayloadEntry/UefiPaylo
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: Benjamin Doron
---
UefiPayloadPkg/UefiPayloadPkg.dec | 6 +++---
UefiPayloadPkg/UefiPayloadPkg.dsc | 1 -
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/UefiPayloadPkg/UefiPayloadPkg.dec
b/UefiPayloadPkg
Adafruit ItsyBitsy M4, using 1 MHz clock and 60 us delay.
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Nate DeSimone
Cc: Chasel Chiu
Signed-off-by: Benjamin Doron
---
.../DxeI2cHdmiDebugSerialPortLib.inf | 2 ++
.../Library/I2cHdmiDebugSerialPortLib/Gmbus.c | 9
Adafruit ItsyBitsy M4, using 1 MHz clock and 60 us delay.
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Nate DeSimone
Cc: Chasel Chiu
Signed-off-by: Benjamin Doron
---
.../DxeI2cHdmiDebugSerialPortLib.inf | 2 ++
.../Library/I2cHdmiDebugSerialPortLib/Gmbus.c | 11
Thanks, Isaac. Are these two S3 series ready to merge, or did I have more
review to address?
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still desired.
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Liming Gao
Cc: Eric Dong
Signed-off-by: Benjamin Doron
---
.../AdvancedFeaturePkg/AdvancedFeaturePkg.dsc | 1 +
.../Include/AdvancedFeatures.dsc | 4 +
.../Include/AdvancedFeaturesPc
I agree this is good, but an alternate option is to
EfiBootManagerGetBootManagerMenu(), as I've implemented here:
https://edk2.groups.io/g/devel/topic/84876596. Then, the boot menu is
guaranteed to have it's boot option.
However, as Nate mentioned, there's the issue of
https://github.com/tiano
: Benjamin Doron
---
.../FspWrapperHobProcessLib.c | 69 ++-
.../PeiFspWrapperHobProcessLib.inf| 2 +
.../Include/Dsc/CorePeiInclude.dsc| 2 +
.../Include/Fdf/CorePostMemoryInclude.fdf | 4 ++
4 files changed, 76 insertions(+), 1 deletion
compatible debug stack.
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Chasel Chiu
Cc: Jeremy Soller
Cc: Sai Chaganty
Cc: Isaac Oram
Signed-off-by: Benjamin Doron
---
.../PeiFspMiscUpdUpdateLib.c | 12 +-
.../PeiSaPolicyUpdate.c | 12
: Nate DeSimone
Cc: Ankit Sinha
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Liming Gao
Signed-off-by: Benjamin Doron
---
.../S3FeaturePkg/Include/PostMemory.fdf | 12 ++
.../S3FeaturePkg/Include/PreMemory.fdf| 8 +-
.../S3FeaturePkg/Include/S3Feature.dsc| 36
: Benjamin Doron
---
Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc| 1 +
Platform/Intel/MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf | 1 +
2 files changed, 2 insertions(+)
diff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc
b/Platform/Intel/MinPlatformPkg
irrelevant. If it's simply
the finalised implementation, I think this isn't worth a diff against
the reflog.
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Chasel Chiu
Cc: Liming Gao
Cc: Eric Dong
Cc: Jeremy Soller
Signed-off-by: Benjamin Doron
Benjamin
Box.inf
>
> Are not S3 specific and belong with common stage 4 or 5 content. It seems
> many features could require them. DSC can deal with duplicates, but FDF
> would fail if there were collisions.
>
> S3Feature.dsc
> - Remove commented out code
>
> Regards,
> Isaac
&
the PchAcpiBaseSet()... constructor?
Specifically, EIP points at `test ebx, 0xff00`. Note that this means
that re-entry actually succeeds. Maybe.
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Liming Gao
Cc: Eric Dong
Signed-off-by: Benjamin Doron
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Nate DeSimone
Cc: Chasel Chiu
Signed-off-by: Benjamin Doron
---
.../DxeAspireVn7Dash572GAcpiTableLib.c| 5
.../BoardAcpiLib/DxeBoardAcpiTableLib.inf | 1 +
.../SmmAspireVn7Dash572GAcpiEnableLib.c | 8 -
.../Library/BoardEcLib
: Nate DeSimone
Cc: Ankit Sinha
Signed-off-by: Benjamin Doron
---
.../Include/Library/BoardEcLib.h | 5 +-
.../Library/BoardEcLib/BoardEcLib.inf | 1 +
.../Library/BoardEcLib/EcCommands.c | 36 ++
.../BoardInitLib/PeiAspireVn7Dash572GDetect.c | 47
nsume the variable in the appropriate place.
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Chasel Chiu
Cc: Nate DeSimone
Signed-off-by: Benjamin Doron
---
.../PeiBoardPolicyUpdate.c| 56 ++-
.../PeiSiliconPolicyUpdateLibFsp.inf | 7 +-
.../Include/BoardConfigNvD
Add a callback to notify the EC of platform resets.
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Chasel Chiu
Cc: Nate DeSimone
Signed-off-by: Benjamin Doron
---
.../Library/BoardInitLib/DxeBoardInitLib.c| 92 ++-
.../Library/BoardInitLib/DxeBoardInitLib.inf | 4 +
2 files
board.
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Nate DeSimone
Cc: Chasel Chiu
Signed-off-by: Benjamin Doron
---
.../AspireVn7Dash572G/OpenBoardPkg.dsc| 63 +++
.../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 59 ++---
2 files changed, 74 insertions(+), 48
Perform EC read and write via SystemIO when EmbeddedControl is
unavailable. Not properly tested yet.
Re-sync against coreboot port.
Does not yet handle SMM traps. In-progress.
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Nate DeSimone
Cc: Chasel Chiu
Signed-off-by: Benjamin Doron
---
.../Acpi
Remove unused includes, LibraryClasses and update a comment or two.
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Chasel Chiu
Cc: Nate DeSimone
Signed-off-by: Benjamin Doron
---
.../PcieDeviceTable.c | 1 -
.../PeiBoardPolicyUpdate.c | 6
s now predictable, though more work is required
to finalise the desired output buffer correspondence with board ID.
Implement a HII form to control BIOS lock functionality. Other
configuration options planned.
Benjamin Doron (7):
KabylakeOpenBoardPkg/AspireVn7Dash572G: Cleanup library inc
: Sai Chaganty
Cc: Isaac Oram
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Chasel Chiu
Signed-off-by: Benjamin Doron
---
...ptExecutorDxeI2cHdmiDebugSerialPortLib.inf | 48 ++
.../DxeI2cHdmiDebugSerialPortLib.inf | 8 +-
.../DxeSmmI2cHdmiDebugSerialPortLib.c | 2 -
.../Li
ns to have the desired default. Presently, DEBUG() works in SEC
phase.
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Chasel Chiu
Cc: Liming Gao
Cc: Eric Dong
Signed-off-by: Benjamin Doron
---
.../Library/SecFspWrapperPlatformSecLib/PlatformInit.c
HDMI port can be used with I2cHdmiDebugSerialPortLib, for debugging in
all phases.
Cc: Chasel Chiu
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Nate DeSimone
Cc: Ankit Sinha
Signed-off-by: Benjamin Doron
---
.../AspireVn7Dash572G/OpenBoardPkg.dsc| 85
for my second planned GSoC
2022 project.
These are enhancements to Nate's series here:
https://edk2.groups.io/g/devel/message/90591.
Benjamin Doron (3):
MinPlatformPkg,WhiskeylakeOpenBoardPkg/SecFspWrapperPlatformSecLib:
First BoardInitLib
[WIP] KabylakeOpenBoardPkg/I2cHdmiDebugSerialPo
compatible debug stack.
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Chasel Chiu
Cc: Jeremy Soller
Cc: Sai Chaganty
Cc: Isaac Oram
Signed-off-by: Benjamin Doron
---
.../PeiFspMiscUpdUpdateLib.c | 12 +++-
.../PeiSaPolicyUpdate.c | 12
: Benjamin Doron
---
.../FspWrapperHobProcessLib.c | 69 ++-
.../PeiFspWrapperHobProcessLib.inf| 2 +
.../Include/Dsc/CorePeiInclude.dsc| 2 +
.../Include/Fdf/CorePostMemoryInclude.fdf | 2 +
4 files changed, 74 insertions(+), 1 deletion
: Nate DeSimone
Cc: Ankit Sinha
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Liming Gao
Signed-off-by: Benjamin Doron
---
.../S3FeaturePkg/Include/PostMemory.fdf | 13 ++
.../S3FeaturePkg/Include/PreMemory.fdf| 8 +-
.../S3FeaturePkg/Include/S3Feature.dsc| 38
Ni
Cc: Rangasai V Chaganty
Cc: Isaac Oram
Signed-off-by: Benjamin Doron
---
.../PeiSmmControlLib/PeiSmmControlLib.c | 309 ++
.../PeiSmmControlLib/PeiSmmControlLib.inf | 34 ++
.../Include/Library/SmmControlLib.h | 26 ++
.../Intel/IntelSiliconPkg
tree using the MCH SMRAMC register.
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Isaac Oram
Signed-off-by: Benjamin Doron
---
.../PeiSmmAccessLibSmramc/PeiSmmAccessLib.c | 430 ++
.../PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf | 36 ++
2 files
: Chasel Chiu
Cc: Sai Chaganty
Cc: Heng Luo
Signed-off-by: Benjamin Doron
---
.../CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc | 1 +
.../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../AspireVn7Dash572G/OpenBoardPkgPcd.dsc| 1
irrelevant. If it's simply
the finalised implementation, I think this isn't worth a diff against
the reflog.
Benjamin Doron (6):
{Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition
IntelSiliconPkg/Feature/SmmAccess: Implement PPI with chipset support
IntelSiliconPkg/F
Follow AcpiPlatformDxe (from which this module is derived) and install
all ACPI tables added by board.
Cc: Chasel Chiu
Cc: Nate DeSimone
Signed-off-by: Benjamin Doron
---
.../Acpi/BoardAcpiDxe/BoardAcpiDxe.c | 15 ++-
.../Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
Follow AcpiPlatformDxe (from which this module is derived) and install
all ACPI tables added by board.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Rangasai V Chaganty
Cc: Deepika Kethi Reddy
Cc: Kathappan Esakkithevar
Signed-off-by: Benjamin Doron
---
.../Acpi/BoardAcpiDxe/BoardAcpiDxe.c
Follow AcpiPlatformDxe (from which this module is derived) and install
all ACPI tables added by board.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Liming Gao
Cc: Eric Dong
Signed-off-by: Benjamin Doron
---
Platform/Intel/MinPlatformPkg/Acpi/MinDsdt/MinDsdt.c | 10 ++
Platform/Intel
Follow AcpiPlatformDxe (from which this module is derived) and install
all ACPI tables added by board.
Cc: Chasel Chiu
Cc: Nate DeSimone
Signed-off-by: Benjamin Doron
---
.../Acpi/BoardAcpiDxe/BoardAcpiDxe.c | 15 ++-
.../Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
.
Tested with KabylakeOpenBoardPkg, the Aspire VN7-572G's BoardAcpiTables
are successfully installed.
Benjamin Doron (4):
KabylakeOpenBoardPkg/Acpi: BoardAcpiDxe also installs all
PcdAcpiTableStorageFile
CometlakeOpenBoardPkg/Acpi: BoardAcpiDxe also installs all
PcdAcpiTableStorag
mation should be "information" in multiple instances
> - GetPeiMemSize - Generally we would prefer #defines in .h or near top of
> the file after includes and before function prototypes and implementations.
> - Resolve ToDo
>
> S3Pei.c
> - Resolve ToDo and TODO/TEST
>
&g
sing? I thought those platforms are quite old and
> no one is using them.
>
> > -Original Message-
> > From: Oram, Isaac W
> > Sent: Tuesday, August 30, 2022 6:27 AM
> > To: Benjamin Doron ; devel@edk2.groups.io
> > Cc: Desimone, Nathaniel L ; Sinha,
>
ress);
> I think that you should be able to use that PCD for any Intel
> chipset/silicon for the foreseeable future.
>
> I would prefer to see contents of sections in INF files indented, but it
> is a nit.
>
> Regards,
> Isaac
>
> -Original Message-----
> From: de
compatible debug stack.
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Chasel Chiu
Cc: Jeremy Soller
Cc: Sai Chaganty
Cc: Isaac Oram
Signed-off-by: Benjamin Doron
---
.../PeiFspMiscUpdUpdateLib.c | 12 +++-
.../PeiSaPolicyUpdate.c | 12
: Benjamin Doron
---
.../FspWrapperHobProcessLib.c | 70 ++-
.../PeiFspWrapperHobProcessLib.inf| 2 +
.../Include/Dsc/CorePeiInclude.dsc| 4 ++
.../Include/Fdf/CorePostMemoryInclude.fdf | 4 ++
4 files changed, 79 insertions(+), 1 deletion
compatibility shim.
Tested, working on Kabylake. Further testing required after the refactor
for compatibility.
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Isaac Oram
Signed-off-by: Benjamin Doron
---
.../BaseIntelCompatShimLibCfl.c | 24
: Nate DeSimone
Cc: Ankit Sinha
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Liming Gao
Signed-off-by: Benjamin Doron
---
.../S3FeaturePkg/Include/PostMemory.fdf | 15 ++
.../S3FeaturePkg/Include/PreMemory.fdf| 8 +-
.../S3FeaturePkg/Include/S3Feature.dsc| 42
tree using the MCH SMRAMC register.
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Isaac Oram
Signed-off-by: Benjamin Doron
---
.../PeiSmmAccessLibSmramc/PeiSmmAccessLib.c | 430 ++
.../PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf | 41 ++
2 files
irrelevant. If it's simply
the finalised implementation, I think this isn't worth a diff against
the reflog.
Benjamin Doron (5):
IntelSiliconPkg/Feature/PeiSmmAccessLibSmramc: Implement chipset
support
Silicon/Intel: Port SmmControl protocol to PPI for S3
S3FeaturePkg: Implement
mmand I use: git format-patch -M --thread origin/master
> --cover-letter --subject-prefix="edk2-devel][edk2-platforms][PATCH V1"
>
> Regards,
> Isaac
>
> -Original Message-
> From: Benjamin Doron
> Sent: Monday, July 25, 2022 10:12 AM
> To: devel@edk2.g
tel's
logo.
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Eric Dong
Cc: Dandan Bi
Cc: Liming Gao
Signed-off-by: Benjamin Doron
---
Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
| 8 -
Features/Intel/UserInterface/Logo
second bug can be seen: version 2 does not challenge for
the password. An RSC handler to hook UiApp entry is probably needed, as
in version 1.
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Liming Gao
Cc: Dandan Bi
Signed-off-by: Benjamin Doron
---
Feat
successfully write to the debug buffer.
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Liming Gao
Cc: Eric Dong
Signed-off-by: Benjamin Doron
---
Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc | 1 +
Features/Intel/AdvancedFeaturePkg/Include
Signed-off-by: Benjamin Doron
---
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
| 12 ++-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
Allocate memory to use on S3 resume.
TODO: Size calculation, confirm implementation goes in this module.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Isaac Oram
Cc: Liming Gao
Cc: Eric Dong
Signed-off-by: Benjamin Doron
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables
Follow-up commits to MinPlatform (AcpiPlatform and
PeiFspWrapperHobProcessLib for memory) and FSP-related board libraries
required for successful S3 resume.
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Sai Chaganty
Cc: Isaac Oram
Cc: Liming Gao
Signed-off-by: Benjamin Doron
---
Features/Intel
Ni
Cc: Rangasai V Chaganty
Cc: Isaac Oram
Signed-off-by: Benjamin Doron
---
Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibCfl/BaseIntelCompatShimLibCfl.c
| 28 ++
Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibCfl/BaseIntelCompatShimLibCfl.inf
| 24
V Chaganty
Cc: Isaac Oram
Signed-off-by: Benjamin Doron
---
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.c
| 431
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf
| 42
ted on the AspireVn7Dash572G board (Skylake/Kabylake). S3 resume
back into to the OS is successful. This is a work in-progress, so more
debugging and security testing may still be needed.
Benjamin Doron (5):
IntelSiliconPkg/Feature/PeiSmmAccessLibSmramc: Implement chipset
support
Silicon/I
.
Best regards,
Benjamin
On Mon, 18 Jul 2022 at 16:33, Benjamin Doron
wrote:
> Hi all,
> I've been working on implementing S3 resume support for MinPlatform during
> the past few weeks. Presently, the last line of code that I know will
> execute on resume flows is
> https://githu
Hi all,
I've been working on implementing S3 resume support for MinPlatform during
the past few weeks. Presently, the last line of code that I know will
execute on resume flows is
https://github.com/tianocore/edk2/blob/master/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c#L878
- right before tra
shows the TianoCore log. An improved revision of the debug library used
in several coreboot-related EDK2 forks, including MrChromebox's.
Previous revisions also tested on an Acer Aspire VN7-572G laptop.
Cc: Guo Dong
Cc: Ray Ni
Cc: Maurice Ma
Cc: Benjamin You
Cc: Sean Rhodes
Signed-off-by
Forgot to mention: I suspect that logging in SEC might work if
BoardAfterTempRamInit() is called earlier in
MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c:PlatformInit().
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Hi Nate,
It looks like you have the SerialPortLib linked into the wrong RSC module in
the SMM instance. It should be linked into the handler, as it is for the other
phases here. You probably just copied the wrong module name, but this is why
logging isn't working.
In general, I don't know why P
fields differ between platforms, such as GPE0 address and the
removal of PM{1,2}* addresses, which should be handled in a follow-up.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Isaac Oram
Cc: Liming Gao
Cc: Eric Dong
Cc: Ankit Sinha
Signed-off-by: Benjamin Doron
---
Platform/Intel/M
v3:
- Rename gCbConsole to mCbConsole
- Add comments about the cb_cbmem_ref structure in coreboot table
- Ensure that no single debug message could overflow a very small buffer
- Set overflow flag preemptively in the event that the cursor must be zeroed
after a message reaches the tail of the buff
shows the TianoCore log. An improved revision of the debug library used
in several coreboot-related EDK2 forks, including MrChromebox's.
Previous revisions also tested on an Acer Aspire VN7-572G laptop.
Cc: Guo Dong
Cc: Ray Ni
Cc: Maurice Ma
Cc: Benjamin You
Cc: Sean Rhodes
Signed-off-by
On Wed, Jun 1, 2022 at 05:33 AM, Gerd Hoffmann wrote:
>
> Hmm. Maybe it's time to tackle the log performance problem for virtual
> machines? Create a debug log device with DMA support, so we don't need
> a vmexit for every single character we want log?
Of course, that doesn't work for native sys
Hi Guo,
Dumping some of the coreboot table shows that some smaller entries/data (such
as build information) are inserted inline while larger entries use the
cb_cbmem_ref structure. This may answer why some users of FindCbTag() assign
the returned pointer directly to their requested structure, wh
There actually is a possibility that even one message would overflow the
buffer. Unlike the other debug library stack I wrote (which I might work on
upstreaming during GSoC), where buffers are specified in kilobyte multiples,
the user specifies CBMEM console size as a number of bytes. Some of th
Hi Theo and Nate,
I took a brief look at this myself, because having an emulated environment
would help me with my project. I didn't know then that QemuOpenBoardPkg was an
accepted project this year. OvmfPkg is large, I'm unfamiliar with QEMU's
codebase and I'm only minimally familiar with Intel
shows the TianoCore log. An improved revision of the debug library used
in several coreboot-related EDK2 forks, including MrChromebox's.
Previous revisions also tested on an Acer Aspire VN7-572G laptop.
Cc: Guo Dong
Cc: Ray Ni
Cc: Maurice Ma
Cc: Benjamin You
Cc: Sean Rhodes
Signed-off-by
shows the TianoCore log. An improved revision of the debug library used
in several coreboot-related EDK2 forks, including MrChromebox's.
Previous revisions also tested on an Acer Aspire VN7-572G laptop.
Cc: Guo Dong
Cc: Ray Ni
Cc: Maurice Ma
Cc: Benjamin You
Cc: Sean Rhodes
Signed-off-by
Hi Nate,
Thanks! I've looked at the basics of I2C, but I've seen from the iGFX PRM that
GMBUS implements some registers and error handling the NAKs differently, but I
guess that I'll be dealing with that later.
Yeah, I was thinking that if we wanted debug up as soon as possible, then the
iGFX B
a good project proposal? I'd appreciate any feedback.
Thanks.
Best regards,
Benjamin
On Tue, 22 Mar 2022 at 17:14, Benjamin Doron
wrote:
> Hi all,
> I'm Benjamin Doron. Last year, I worked on a board port to MinPlatform.
> This year, I hope to pick up where I left off and he
Hi all,
I'm Benjamin Doron. Last year, I worked on a board port to MinPlatform.
This year, I hope to pick up where I left off and help improve MinPlatform
by adding support for S3 resume (time permitting and if my skills are
sufficient, etc). Previously, I worked a little on coreboot (mai
back to it when I can if
upstream/coreboot's fork wants.
Regards,
Benjamin
On Fri., Jan. 28, 2022, 4:38 p.m. Sean Rhodes,
wrote:
> From: Benjamin Doron
>
> Tested on QEMU, dumping the appropriate memory region in UEFI shell
> shows the TianoCore log. `find_cb_subtable` is s
Remove unused includes, LibraryClasses and update a comment or two.
Cc: Chasel Chiu
Cc: Nate DeSimone
Signed-off-by: Benjamin Doron
---
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c
| 1 -
Platform
nsume the variable in the appropriate place.
Cc: Chasel Chiu
Cc: Nate DeSimone
Signed-off-by: Benjamin Doron
---
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c
| 51 ++-
Platform/Intel/KabylakeOpenBoa
Add a callback to notify the EC of platform resets.
Cc: Chasel Chiu
Cc: Nate DeSimone
Signed-off-by: Benjamin Doron
---
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.c
| 90 +++-
Platform/Intel/KabylakeOpenBoardPkg
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