From: Abner Chang
Set SettingsObject URI in @Redfish.Settings resource as the config
language which is the same as the config language of parent URI
that mandates @Redfish.Settings.
With this, we can find the config language of the properties in
SettingsObject URI.
Signed-off-by: Abner Chang
Cc
Gentle reminder, please review and merge the patch.
On 08-03-2024 12:52, Abdul Lateef Attar via groups.io wrote:
Caution: This message originated from an External Source. Use proper caution
when opening attachments, clicking links, or responding.
From: Abdul Lateef Attar
PR : https://github
Hi Gerd,
Thanks,
Chao
On 2024/3/20 18:16, Gerd Hoffmann wrote:
On Mon, Mar 18, 2024 at 04:28:17PM +0100, Gerd Hoffmann wrote:
On Sat, Mar 16, 2024 at 10:17:00AM +0800, lixianglai wrote:
Hi Gerd:
On Mon, Mar 11, 2024 at 02:39:31AM -0700, Chao Li wrote:
This library for PEI phase, and obtains
Hi Liming,
Another friendly ping, can you review these patches? 2 RBs and
conversation has died down.
Thanks,
Oliver
On 3/13/2024 10:33 AM, Oliver Smith-Denny wrote:
Hi Liming,
Friendly ping, can you please review this patchset?
Thanks,
Oliver
On 3/11/2024 2:29 PM, Oliver Smith-Denny wrote:
hi,
In the windows10 environment, set the RTC_EN bit before entering S5 from S0
after pressing the power button to turn on the RTC Wake up function.
At https://github.com/tianocore/e dk2-platforms/blob/bb44e786e7a
7cc618e985b3e0b93a9f33a4b7ea2/ Platform/Intel/Vlv2TbltDeviceP
kg/PlatformSmm/Plat
Hi Saloni,
Sorry for the drop in.
Is there any schedule for pull in the HTTP Proxy changes from edk2-staging to
edk2?
Thanks a lot!
Best Regards
Vivian Shi
American Megatrends Information Technology (Kunshan) Co., Ltd.
Tel: +86-512-57360204 #259
From: Vivian Shi (石丽)
Sent: Tuesday, January 30
From: Xiong Yining
Provide functions to check for memory information:
- amount of memory nodes
- memory address
- NUMA node id for memory
Values are read from TF-A using platform specific SMC calls.
Signed-off-by: Xiong Yining
Signed-off-by: Chen Baozi
Signed-off-by: Marcin Juszkiewicz
---
We have SbsaQemuHardwareInfoLib to ask for hardware details. No need to
parse DeviceTree anymore.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 6 ++
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 5 ++---
.../SbsaQemu/Library/SbsaQemu
There is no need for EDK2 to know that there is DeviceTree around.
All hardware information is read using functions from
SbsaQemuHardwareInfoLib library.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 1 -
1 file changed, 1 deletion(-)
diff --git a/Platform/Qemu/Sbs
This library provides functions to check for hardware information.
For now it covers CPU ones:
- amount of cpu cores
- MPIDR value for cpu core
- NUMA node id for cpu core
Values are read from TF-A using platform specific SMC calls.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/S
We want to stop parsing DeviceTree to gather hardware information.
Instead we ask TF-A for those details using SMC calls. On real hardware
platform it could be asking on-board Embedded Controller.
Hardware information (CPU, Memory) is now in SbsaQemuHardwareInfoLib
together with new code for hand
W dniu 19.03.2024 o 17:53, Ard Biesheuvel pisze:
new file mode 100644
index ..e621c422bd40
--- /dev/null
+++
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf
@@ -0,0 +1,31 @@
+#/* @file
+#
+# Copyright (c) 2024, Linaro Ltd. All rights reserved.
+#
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4735
Should not call HiiGetBrowserData() and HiiSetBrowserData() in FORM_OPEN
call back function.
Those APIs are called within OpalHiiSetBrowserData/OpalHiiGetBrowserData
which have been used by OpalHii.c.
1. Move HiiPopulateMainMenuForm() into
On Mon, Mar 18, 2024 at 04:28:17PM +0100, Gerd Hoffmann wrote:
> On Sat, Mar 16, 2024 at 10:17:00AM +0800, lixianglai wrote:
> > Hi Gerd:
> > > On Mon, Mar 11, 2024 at 02:39:31AM -0700, Chao Li wrote:
> > >> This library for PEI phase, and obtains the QemuFwCfg base address by
> > >> directly parsi
On Wed, Mar 20, 2024 at 08:41:41AM +, Sun, CepingX wrote:
>
> On Thursday, March 14, 2024 5:31 PM Gerd Hoffmann wrote:
> > Load, measure and cache all fw_cfg entries we care about early in the PEI
> > phase
> > (or SEC phase for pei-less builds), so we can
> > (a) easily have a fixed order,
Hi Ard and Gerd,
Thanks,
Chao
On 2024/3/15 17:54, Chao Li wrote:
Hi Ard,
On 2024/3/15 17:51, Ard Biesheuvel wrote:
On Fri, 15 Mar 2024 at 10:49, Chao Li wrote:
Hi Gerd,
Thanks,
Chao
On 2024/3/15 17:33, Gerd Hoffmann wrote:
On Mon, Mar 11, 2024 at 05:39:02PM +0800, Chao Li wrote:
Add a
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4735
Should not call HiiGetBrowserData() and HiiSetBrowserData() in FORM_OPEN
call back function.
Those APIs are called within OpalHiiSetBrowserData/OpalHiiGetBrowserData
which have been used by OpalHii.c.
1. Move HiiPopulateMainMenuForm() into
Added LoongArch64 CPU driver into CpuDxe.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
Co-authored-by: Dongyan Qian
---
UefiCpuPkg/CpuDxe/CpuDxe.inf | 23 +-
UefiCpuPkg/
Added LoongArch multiprocessor initialization instance into MpInitLib.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 20 +-
.../Library/MpInitLib/LoongArch64/Dx
Add a new base library named CpuMmuInitLib and add a LoongArch64
instance with in the library.
It is the consumer of the CpuMmuLib.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
Co-autho
Add a new base library named CpuMmuLib and add a LoongArch64 instance
with in the library.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
Co-authored-by: Dongyan Qian
Co-authored-by: Xia
This file provide the CPU MMU configure and initialize interface, it
will consumes by CpuMmuLib to configure or initialize the MMU.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Sami Mujawar
Cc:
Added PcdCpuExceptionVectorBaseAddress use for storing the CPU exception
vector base address. This PCD can be be populated at build time or
changed at runtime.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Acked-by:
Add a new header file CpuMmuLib.h, whitch is referenced from
ArmPkg/Include/Library/ArmMmuLib.h. Currently, only support for
LoongArch64 is added, and more architectures can be accommodated in the
future.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Ger
Added LoongArch exception handler into CpuExceptionHandlerLib.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
---
.../DxeCpuExceptionHandlerLib.inf | 23 +-
.../LoongArch/Dx
Add the LoongArch64 CPU Timer instance to CpuTimerLib, using CPUCFG 0x4
and 0x5 for Stable Counter frequency.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
.../Library/CpuTimerLib/BaseCpuTimerLib.inf | 15 +-
Some of the order is not in alphabetical, reorder.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4726
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Acked-by: Gerd Hoffmann
---
UefiCpuPkg/CpuDxe/CpuDxe.inf | 16
1 file changed, 8 insertions(+), 8 d
Some of the order is not in alphabetical, reorder.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4726
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Acked-by: Gerd Hoffmann
---
UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 29 ++-
UefiCpuPkg/Libra
Some of the order is not in alphabetical, reorder.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4726
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Acked-by: Gerd Hoffmann
---
.../DxeCpuExceptionHandlerLib.inf | 20 +--
.../PeiCpuExcept
Some of the order is not in alphabetical, reorder.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4726
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Acked-by: Gerd Hoffmann
---
UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf | 2 +-
1 file changed, 1 insertion(+
This patch set adjusted some order in UefiCpuPig alphabetically, added
LoongArch libraries and drivers into UefiCpuPkg, it is a continuation of
the first patch series v8 submitted at
https://edk2.groups.io/g/devel/message/114526.
And also separated from https://edk2.groups.io/g/devel/message/11658
On Thursday, March 14, 2024 5:31 PM Gerd Hoffmann wrote:
> Load, measure and cache all fw_cfg entries we care about early in the PEI
> phase
> (or SEC phase for pei-less builds), so we can
> (a) easily have a fixed order, and
> (b) store them all in HOBs?
>
> Which implies SEC/PEI must read a
Hi All,
Could you help review this change? Very Appreciate.
Best regards,
Xianglei
-Original Message-
From: Cai, Xianglei
Sent: Tuesday, March 12, 2024 1:13 PM
To: devel@edk2.groups.io
Cc: Cai, Xianglei ; Wu, Hao A ; Ni,
Ray ; Liming Gao ; Huang, Jenny
; Shih, More
Subject: [PATCH 1
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