[AMD Official Use Only - General]
Hi Jeff, Sami,
I'm not reviewer, just providing the opinion.
How about making it generic(generic to integer argument) instead of single
integer argument.
INUINT64 IntegerArgument
IN UINT64
The IO Remapping Table, Platform Design Document, Revision E.e,
Sept 2022 (https://developer.arm.com/documentation/den0049/ee)
added flags in SMMUv3 node for validity of ID mappings for MSIs
related to control interrupts.
It makes one small addition to SMMUv3 nodes to
describe MSI support independe
The Visual Studio Windows debugger will only load symbols for PE/COFF images
that Windows is aware of. Therefore, to enable source level debugging, all
PEI/DXE modules must be loaded via LoadLibrary() or LoadLibraryEx() and the
the instance in memory created by LoadLibrary() must be the one that is
On Fri, Sep 22, 2023 at 15:35:03 +0100, Sami Mujawar wrote:
> This patch series provides the following updates:
> - The patches 1 & 2 add the new fields introduced
> in MADT (APIC table) by ACPI 6.5 and the patch
> 7/11 updates the Acpiview MADT parser accordingly.
> - The patches 3, 4 & 5 adds
On Fri, Sep 22, 2023 at 16:18:17 +0200, PierreGondois wrote:
> From: Pierre Gondois
>
> The IsaRange parameter in:
> - AmlCodeGenRdDWordIo()
> - AmlCodeGenRdQWordIo()
> is an hard-coded value. Define an enum for IsarRanges
> and use it.
>
> Suggested-by: Leif Lindholm
> Signed-off-by: Pierre Go
On Wed, Sep 20, 2023 at 17:55:39 +0200, Marcin Juszkiewicz wrote:
> Those changes float around whenever I do some changes in code. Time to
> send them for merge and stop bothering.
>
> Marcin Juszkiewicz (2):
> Silicon/SbsaQemu: drop duplicated Pcd
> Silicon/SbsaQemu: fix comment to show prope
On Wed, Sep 20, 2023 at 16:33:16 +0200, Marcin Juszkiewicz wrote:
> Arm BSA (Base System Architecture) specification requires Armv8.1+ cpus
> to have non-secure EL2 virtual timer. Which we lacked.
>
> In previous week I wrote a small patch to QEMU which enabled it for SBSA
> Reference Platform. Le
Greetings,
A week long collaboration between me and Gpt yielded this functioning mock of a
sample UEFI Protocol:
struct SampleProtocol {
INTN (*GetVersion)(
);
};
struct MockSampleProtocol : public SampleProtocol {
static MockSampleProtocol *instance;
MockSampleProtocol (
)
{
// Assign th
Hi Sami,
Thanks for the update:
Reviewed-by: Pierre Gondois
Regards,
Pierre
On 9/22/23 16:35, Sami Mujawar wrote:
This patch series provides the following updates:
- The patches 1 & 2 add the new fields introduced
in MADT (APIC table) by ACPI 6.5 and the patch
7/11 updates the Acpiview M
Hi Sami,
Thanks for the update:
Reviewed-by: Pierre Gondois
Regards,
Pierre
On 9/22/23 16:41, Sami Mujawar wrote:
This patch series updates the FVP platform firmware
to add support for dynamically generating CPU nodes
in AML and also reports the TRBE interrupt in the
MADT GICC structure. The l
When ETE is enabled in the FVP model the firmware can check
the debug feature register ID_AA64DFR0_EL1.TraceVer field
to identify the presence of FEAT_ETE and add an ETE device
to the CPU node in the AML CPU hierarchy. This enables the
Operating System driver to probe and enable ETE support.
Note
When TRBE is enabled the FVP model uses the PPI 15
(i.e. INT ID 31) as the TRBE interrupt.
Ref: https://www.kernel.org/doc/Documentation/
devicetree/bindings/arm/arm,trace-buffer-extension.yaml
Therefore, check the debug feature register
ID_AA64DFR0_EL1.TraceBuffer field to see if TRBE is
enabled
Add support to dynamically generate the CPU nodes in SSDT.
Signed-off-by: Sami Mujawar
---
Notes:
v3:
- No code change from v2 patch series. [SAMI]
v2:
- No code change from v1 patch series. [SAMI]
Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManag
This patch series updates the FVP platform firmware
to add support for dynamically generating CPU nodes
in AML and also reports the TRBE interrupt in the
MADT GICC structure. The last patch in the series
enables support for adding an ETE device to the CPU
device nodes in AML.
This patch series dep
Create a helper function to query whether ID_AA64MFR1_EL1 indicates
presence of the Embedded Trace Extension (ETE). This feature is only
visible in AARCH64 state.
Signed-off-by: Sami Mujawar
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Pierre Gondois
---
Notes:
v3:
- New patch in this se
Create a helper function to query whether ID_AA64MFR1_EL1 indicates
presence of the Trace Buffer Extension (TRBE). This feature is only
visible in AARCH64 state.
Signed-off-by: Sami Mujawar
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Pierre Gondois
---
Notes:
v3:
- New patch in this ser
The ACPI 6.5 specification updates the MADT table to add
a new field to GICC for specifying the TRBE interrupt and
also adds support for Online Capable flag to the GICC flags.
The Online Capable flags should be passed transparently
through as specified in the CM_ARM_GICC_INFO.Flags field
and only
The CpcToken has been incorrectly referenced in the
CreateTopologyFromGicC() and always points to the
CPC token in the first GICC Info object.
Therefore, fix this by correctly indexing into the
GicCInfo object array.
Signed-off-by: Sami Mujawar
Reviewed-by: Pierre Gondois
---
Notes:
v3:
Add an Embedded Trace (ET) info object that can be
used to provide information about Embedded Trace
Extension (ETE) or Embedded Trace Module (ETM)
available on a platform.
Although ETE and ETM share the same HID,
ETE has a system register interfaces, unlike
ETM which requires memory mapped registe
The ACPI 6.5 specification updates the minor revision
of the FADT table to 5. Therefore, update the FADT
generator to setup the minor revision for ACPI 6.5.
Signed-off-by: Sami Mujawar
Reviewed-by: Pierre Gondois
---
Notes:
v3:
- No code change from v2 patch series. [SAMI]
This patch series provides the following updates:
- The patches 1 & 2 add the new fields introduced
in MADT (APIC table) by ACPI 6.5 and the patch
7/11 updates the Acpiview MADT parser accordingly.
- The patches 3, 4 & 5 adds TRBE support to the MADT
table generator in DynamicTablesPkg.
- Pat
An Embedded Trace (ET) info object is used to provide
information about an Embedded Trace Extension (ETE) or
an Embedded Trace Module (ETM) available on a platform.
The CM_ARM_ET_INFO object has already been added to the
Arm namespace objects list by a previous patch.
Therefore, update the CM Obj
The ASWG ECR 2303 introduces a new field 'TRBE
interrupt' to GICC structure in ACPI 6.5.
The Trace Buffer Extension (TRBE) interrupt is a
Processor Private interrupt (PPI) and is used to
specify a platform-specific interrupt to signal
TRBE events.
Signed-off-by: Sami Mujawar
Reviewed-by: Pierre
ACPI 6.5 introduces a new filed to the MADT GICC
structure to specify the TRBE interrupt. The TRBE
interrupt is a Processor Private interrupt (PPI)
and is used to specify a platform-specific
interrupt to signal TRBE events.
Therefore, update the MADT GICC structure parser
to parse the new TRBE int
ACPI 6.5 introduces a new filed to the MADT GICC structure
to specify the Trace Buffer Extension (TRBE) interrupt. The
TRBE interrupt is a Processor Private interrupt (PPI) and is
used to specify a platform-specific interrupt to signal TRBE
events.
This field has already been added to the CM_ARM_G
The Coresight Embedded Trace Extension (ETE) feature
can be detected by the platform firmware by examining
the debug feature register ID_AA64DFR0_EL1.TraceVer
field.
The platform configuration manager can then describe
the ETE by creating CM_ARM_ET_INFO object(s) and
referencing these in CM_ARM_GIC
ACPI 6.5 introduces a new filed to the MADT GICC structure
to specify the Trace Buffer Extension (TRBE) interrupt. The
TRBE interrupt is a Processor Private interrupt (PPI) and is
used to specify a platform-specific interrupt to signal TRBE
events.
Therefore, update the CM_ARM_GICC_INFO to reflect
Bugzilla: 3706 'Code First - MADT GICC new flags'
On ARM systems physical CPU hotplug is not supported.
All CPUs are considered present and this is true
throughout the system uptime.
The ECR 2285 introduces a new 'online-capable' flag
in the GICC structure flags in ACPI 6.5, to signal
firmware po
Reviewed-by: Jeff Brasen
> -Original Message-
> From: pierre.gond...@arm.com
> Sent: Friday, September 22, 2023 8:18 AM
> To: devel@edk2.groups.io
> Cc: Sami Mujawar ; Leif Lindholm
> ; Jeff Brasen
> Subject: [PATCH 1/1] DynamicTablesPkg/AmlLib: Define an enum for
> IsaRanges
>
> Exter
From: Pierre Gondois
The IsaRange parameter in:
- AmlCodeGenRdDWordIo()
- AmlCodeGenRdQWordIo()
is an hard-coded value. Define an enum for IsarRanges
and use it.
Suggested-by: Leif Lindholm
Signed-off-by: Pierre Gondois
---
.../Include/Library/AmlLib/AmlLib.h | 28 +++---
Hi Jeff,
Thank out for this patch series.
These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 21/09/2023 09:10 pm, Jeff Brasen wrote:
Use AmlCodeGenRdQWordIo() to generate the I/O range in _CRS instead of
AmlCodeGenRdDWordIo() to cater to the scenarios where
As sbsa-ref does not have DRAM below 4G, it cannot utilize EHCI
that only has 32-bit DMA capablity and sbsa-ref board uses xhci
to replace ehci.
This updates DSDT to match the platform xhci controller with two
usb ports changed from type A to type C.
This also registers the non-discoverable XHCI
This patchset implements XHCI on sbsa-ref board to replace EHCI.
As sbsa-ref does not have DRAM below 4G, it cannot utilize EHCI
that only has 32-bit DMA capablity. Now this board has XHCI as
an available usb controller with 64-bit DMA capablity.
History:
v2 -> v3:
- remained the original USB hi
Hi Jeff,
On 9/21/23 22:10, Jeff Brasen wrote:
Use AmlCodeGenRdQWordIo() to generate the I/O range in _CRS instead of
AmlCodeGenRdDWordIo() to cater to the scenarios where 64-bit
addresses can be used to generate I/O packets over the PCIe bus.
Changes:
v2 - Rebased and set transferEncoding = 8bi
Hi Pierre,
Thank you for the feedback.
Please see my response inline marked [SAMI].
Regards,
Sami Mujawar
On 22/09/2023, 09:56, "Pierre Gondois" mailto:pierre.gond...@arm.com>> wrote:
Hi Sami,
On 9/13/23 14:52, Sami Mujawar wrote:
> When TRBE is enabled the FVP model uses the PPI 15
> (i.
Hi Pierre,
Thank you for the review feedback.
Please see my response inline marked [SAMI].
Regards,
Sami Mujawar
On 22/09/2023, 09:53, "Pierre Gondois" mailto:pierre.gond...@arm.com>> wrote:
Hi Sami,
On 9/13/23 14:49, Sami Mujawar wrote:
> The ACPI 6.5 specification updates the MADT table
Hi Sami,
On 9/13/23 14:52, Sami Mujawar wrote:
When TRBE is enabled the FVP model uses the PPI 15
(i.e. INT ID 31) as the TRBE interrupt.
Ref: https://www.kernel.org/doc/Documentation/
devicetree/bindings/arm/arm,trace-buffer-extension.yaml
Therefore, check the debug feature register
ID_AA64DFR
Hi Sami,
On 9/13/23 14:49, Sami Mujawar wrote:
The ACPI 6.5 specification updates the MADT table to add
a new field to GICC for specifying the TRBE interrupt and
also adds support for Online Capable flag to the GICC flags.
The Online Capable flags should be passed transparently
through as speci
Hi Sami,
I have a minor comment to:
- [PATCH v2 05/11] DynamicTablesPkg: Update MADT generator for ACPI 6.5
Otherwise for the other patches:
Reviewed-by: Pierre Gondois
Regards,
Pierre
On 9/13/23 14:49, Sami Mujawar wrote:
This patch series provides the following updates:
- The patches 1 &
Reviewed-by: Chao Li
Thanks,
Chao
在 2023/9/22 15:27, Dongyan Qian 写道:
Correct relax id from 99 to 100 and added relocation support up to 109
fix gcc14 adds new relocation, and the generated relocation
causes the build and compilation to fail.
REF:https://bugzilla.tianocore.org/show_bug.cgi?id
Correct relax id from 99 to 100 and added relocation support up to 109
fix gcc14 adds new relocation, and the generated relocation
causes the build and compilation to fail.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4559
Cc: Rebecca Cran
Cc: Liming Gao
Cc: Bob Feng
Cc: Yuwei Chen
Cc:
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