On Tue, May 23, 2023 at 02:59:50PM -0700, Tuan Phan wrote:
> Thanks Andrei,
> Sunil, any comments or it is good to go. As this patchset spans across
> MdePkg, UefiCpuPkg and OvmfPkg, do I need to separate it so each package
> maintainer can merge independently?
>
Hi Tuan,
I don't see an issue whe
Today X86 CpuMp PEIM enables the paging in 32bit and 64bit mode for protection
of:
1. Stack overflow
2. Avoid accessing SPI flash after NEM tear down
We could either producing a 32bit PPI for above needs (DxeIpl should not call
this PPI for DxeCore protection in mixed 32PEI+64DXE env) or separat
Dear all,
I'm also porting MMU library of LoongArch64 to EDK2, I added it in to
UefiCpuPkg and make it possible to use the same headers for both the
no-IA32 and no-X64 platforms, and I also saw that IA32 and X64 added the
CpuPageTableLib to UefiCpuPkg, this library are similar to MMU
librarie
Reviewed-by: Chasel Chiu mailto:chasel.c...@intel.com>>
Thanks,
Chasel
From: Desimone, Nathaniel L
Sent: Tuesday, May 23, 2023 5:59 PM
To: Shindo, Miki ; devel@edk2.groups.io
Cc: Chiu, Chasel ; Gao, Liming
; Dong, Eric ; Zhang, Xiaoqiang
Subject: Re: [edk2-platforms:PATCH v2] MinPlatformPk
Thank you, Miki, and Xiaoqiang!
Reviewed-by: Nate DeSimone
From: Shindo, Miki
Date: Tuesday, May 23, 2023 at 5:44 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel , Desimone, Nathaniel L
, Gao, Liming , Dong,
Eric , Zhang, Xiaoqiang
Subject: [edk2-platforms:PATCH v2] MinPlatformPkg: Fix SetLarg
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4454
On Server platform, when the large variable "FspNvsBuffer" is already in the
UEFI variable store and the remaining variable storage space is less than the
large variable size, and also not in OS runtime, then we need to add the size
of th
[AMD Official Use Only - General]
Hi Neo,
I don't see you add the maintainers either in commit message or email CC list.
I added them.
To this patch, Acked-by: Abner Chang
Thanks
Abner
> -Original Message-
> From: Hsueh, Hong-Chih (Neo)
> Sent: Wednesday, May 24, 2023 1:07 AM
> To:
Thanks Andrei,
Sunil, any comments or it is good to go. As this patchset spans across
MdePkg, UefiCpuPkg and OvmfPkg, do I need to separate it so each package
maintainer can merge independently?
On Mon, May 8, 2023 at 10:19 AM Warkentin, Andrei <
andrei.warken...@intel.com> wrote:
> Apologies for
On Tue, 23 May 2023 at 22:36, Oliver Smith-Denny
wrote:
>
> When the AARCH64 CpuDxe attempts to SyncCacheConfig() with the GCD,
> it collects the page attributes as:
>
> EntryAttribute = Entry & TT_ATTR_INDX_MASK
>
> However, TT_ATTR_INDX_MASK only masks the cacheability attributes
> and drops the
If there is no port multiplier, PortMultiplierPort should be converted
to 0 to follow AHCI spec.
The same logic already applied in AtaAtapiPassThruDxe driver.
Signed-off-by: Neo Hsueh
---
MdeModulePkg/Bus/Ata/AhciPei/AhciPeiPassThru.c | 10 ++
1 file changed, 10 insertions(+)
diff --git
Hi Ard,
Thanks. I agree with your plan.
In the future, if we think there is value in enabling paging in 32-bit PEI, we
could add the PPI at that time.
Mike
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Ard
> Biesheuvel
> Sent: Tuesday, May 23, 2023 8:51 AM
> To: deve
On Tue, 23 May 2023 at 17:15, Michael D Kinney
wrote:
>
>
>
> > -Original Message-
> > From: Ard Biesheuvel
> > Sent: Tuesday, May 23, 2023 7:59 AM
> > To: Kinney, Michael D
> > Cc: devel@edk2.groups.io; ler...@redhat.com; Ni, Ray ;
> > Yao, Jiewen ; Gerd Hoffmann
> > ; Taylor Beebe ; Ol
Hi Pedro,
Thank you for the feedback.
Please see my response inline marked [SAMI].
Regards,
Sami Mujawar
On 23/05/2023 02:32 pm, Pedro Falcato wrote:
On Tue, May 23, 2023 at 2:04 PM Sami Mujawar wrote:
The IAR register of the Gic CPU interface is 32 bit, while
the value returned by ArmGicV
Hi Pedro,
Thank you for the feedback.
Please see my response inline marked [SAMI].
Regards,
Sami Mujawar
On 23/05/2023 02:35 pm, Pedro Falcato wrote:
On Tue, May 23, 2023 at 2:04 PM Sami Mujawar wrote:
The data type used by variables representing the
GicInterruptInterfaceBase has been inco
Hi Ard,
Thank you for the feedback.
I will fix this in the v2 series.
Regards,
Sami Mujawar
On 23/05/2023 02:32 pm, Ard Biesheuvel wrote:
On Tue, 23 May 2023 at 15:04, Sami Mujawar wrote:
According to edk2 coding standard specification, Non-Boolean
comparisons must use a compare operator (
Hi Ard,
Thank you for the feedback.
I will fix this in the next series.
Regards,
Sami Mujawar
On 23/05/2023 02:26 pm, Ard Biesheuvel wrote:
On Tue, 23 May 2023 at 15:04, Sami Mujawar wrote:
The EIOR register of the Gic CPU interface is a 32 bit register.
However, the HARDWARE_INTERRUPT_SOU
> -Original Message-
> From: Ard Biesheuvel
> Sent: Tuesday, May 23, 2023 7:59 AM
> To: Kinney, Michael D
> Cc: devel@edk2.groups.io; ler...@redhat.com; Ni, Ray ;
> Yao, Jiewen ; Gerd Hoffmann
> ; Taylor Beebe ; Oliver Smith-
> Denny
> Subject: Re: [edk2-devel] managing memory attribut
On Tue, 23 May 2023 at 16:49, Kinney, Michael D
wrote:
>
> Ard,
>
> I would prefer to keep the IA32 PEI support for OVMF.
>
Sure. But does that imply that all enhancements regarding memory
protections should be introduced there as well?
If so, could you help figure out whether or not running IA3
Ard,
I would prefer to keep the IA32 PEI support for OVMF.
Ray had proposed an idea to introduce a library class to help
with the DXEIPL complexity. Perhaps that can be combines with
this effort.
Mike
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Laszlo
> Ersek
> Se
On Tue, 23 May 2023 at 15:04, Sami Mujawar wrote:
>
> The ArmGicAcknowledgeInterrupt () returns the value
> returned by the Interrupt Acknowledge Register and
> the InterruptID separately in an out parameter.
>
> The function documents the following:
> 'InterruptId is returned separately from the
On Tue, 23 May 2023 at 15:04, Sami Mujawar wrote:
>
> GICD_SGIR is a 32-bit register, of which INTID is bits [3:0]
> and Bits [14:4] is RES0. Since SgiId parameter in the function
> ArmGicSendSgiTo () is UINT8, mask unused bits of SgiId before
> writing to the GICD_SGIR register to prevent acciden
On Tue, 23 May 2023 at 15:04, Sami Mujawar wrote:
>
> The data type used by variables representing the
> GicInterruptInterfaceBase has been inconsistently
> used in the ArmGic driver and the library.
> The PCD defined for the GIC Interrupt interface
> base address is UINT64. However, the data type
On Tue, May 23, 2023 at 2:04 PM Sami Mujawar wrote:
>
> The data type used by variables representing the
> GicInterruptInterfaceBase has been inconsistently
> used in the ArmGic driver and the library.
> The PCD defined for the GIC Interrupt interface
> base address is UINT64. However, the data ty
On Tue, May 23, 2023 at 2:04 PM Sami Mujawar wrote:
>
> The IAR register of the Gic CPU interface is 32 bit, while
> the value returned by ArmGicV2AcknowledgeInterrupt() is
> UINTN. Therefore, typecast the return value to UINTN before
> returning.
Since IAR is 32-bit, doesn't it make sense to ret
On Tue, 23 May 2023 at 15:04, Sami Mujawar wrote:
>
> According to edk2 coding standard specification, Non-Boolean
> comparisons must use a compare operator (==, !=, >, < >=, <=).
> See Section 5.7.2.1 at https://edk2-docs.gitbook.io/
> edk-ii-c-coding-standards-specification/5_source_files/
> 57_
On Tue, 23 May 2023 at 15:04, Sami Mujawar wrote:
>
> The data type used by variables representing the GicDistributorBase
> has been inconsistently used in the ArmGic driver and the library.
> The PCD defined for the GIC Distributor base address is UINT64.
> However, the data types for the variabl
On Tue, 23 May 2023 at 15:04, Sami Mujawar wrote:
>
> The EIOR register of the Gic CPU interface is a 32 bit register.
> However, the HARDWARE_INTERRUPT_SOURCE used to represent the
> interrupt source (Interrupt ID) is typedefed as UINTN, see
> EmbeddedPkg\Include\Protocol\HardwareInterrupt.h
>
>
On Mon, 22 May 2023 at 08:59, Taylor Beebe wrote:
>
> Hi all,
>
> During the EDK2 design meeting on 5/17, Project Mu developers presented
> memory protection
> and DXE Core revisions.
>
> The presentation covered the following topics:
>
> 1. The motivation for improving memory protections
> 2. S
According to edk2 coding standard specification, Non-Boolean
comparisons must use a compare operator (==, !=, >, < >=, <=).
See Section 5.7.2.1 at https://edk2-docs.gitbook.io/
edk-ii-c-coding-standards-specification/5_source_files/
57_c_programming
Therefore, fix the comparison in ArmGicEnableDis
The CPU Interface Identification Register (GICC_IIDR) is a 32-bit
register. Since ArmGicGetInterfaceIdentification () returns the
value read from the GICC_IIDR register, update the return type
for this function to UINT32.
Signed-off-by: Sami Mujawar
---
ArmPkg/Drivers/ArmGic/ArmGicLib.c | 2 +-
The IrqInterruptHandler () and ExitBootServicesEvent () function
declarations were unused. Therefore, remove these declarations.
Signed-off-by: Sami Mujawar
---
ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/ArmPkg/Drivers/ArmGic/ArmGic
GICD_SGIR is a 32-bit register, of which INTID is bits [3:0]
and Bits [14:4] is RES0. Since SgiId parameter in the function
ArmGicSendSgiTo () is UINT8, mask unused bits of SgiId before
writing to the GICD_SGIR register to prevent accidental setting
of the RES0 bits.
Signed-off-by: Sami Mujawar
-
The ArmGicAcknowledgeInterrupt () returns the value
returned by the Interrupt Acknowledge Register and
the InterruptID separately in an out parameter.
The function documents the following:
'InterruptId is returned separately from the register
value because in the GICv2 the register value contains
The IAR register of the Gic CPU interface is 32 bit, while
the value returned by ArmGicV2AcknowledgeInterrupt() is
UINTN. Therefore, typecast the return value to UINTN before
returning.
Signed-off-by: Sami Mujawar
---
ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c | 2 +-
1 file changed, 1 insertion(
The Software Generated Interrupt Register (GICD_SGIR) is a
32 bit register with the following bit assignment:
TargetListFilter, bits [25:24]
CPUTargetList, bits [23:16]
NSATT, bit [15]
SGIINTID, bits [3:0]
Therefore, modify the TargetListFilter, CPUTargetList,
SGI Interrupt ID parameters o
The data type used by variables representing the
GicInterruptInterfaceBase has been inconsistently
used in the ArmGic driver and the library.
The PCD defined for the GIC Interrupt interface
base address is UINT64. However, the data types
for the variables used is UINTN, INTN, and at
some places UIN
According to the GIC architecture version 3 and 4 specification,
the maximum number of INTID bits supported in the CPU interface
is 24.
Considering this the RegShift variable is not required to be more
than 8 bits. Therefore, make the RegShift variable type to UINT8.
Also add necessary typecasts w
The data type used by variables representing the GicDistributorBase
has been inconsistently used in the ArmGic driver and the library.
The PCD defined for the GIC Distributor base address is UINT64.
However, the data types for the variables used is UINTN, INTN, and
at some places UINT32.
Therefore
Although the maximum interrupt ID on GicV2 is 10bit
and for GicV3/4 is 24bit, and that the IAR and EOIR
registers of the Gic CPU interface are 32 bit; the
typedef HARDWARE_INTERRUPT_SOURCE is defined as
UINTN in
EmbeddedPkg\Include\Protocol\HardwareInterrupt.h
Therefore, use UINTN for Gic Interrup
The EIOR register of the Gic CPU interface is a 32 bit register.
However, the HARDWARE_INTERRUPT_SOURCE used to represent the
interrupt source (Interrupt ID) is typedefed as UINTN, see
EmbeddedPkg\Include\Protocol\HardwareInterrupt.h
Therfore, typecast the interrupt ID (Source) value to UINT32
bef
Bugzilla: Bug 3399 (https://bugzilla.tianocore.org/show_bug.cgi?id=3399)
This patch series address the issues reported in
https://bugzilla.tianocore.org/show_bug.cgi?id=3399
and also has general improvements and fixes for other
issues in the Arm GIC Library and driver.
This patch series is expect
Reviewed-by: Ray Ni
> -Original Message-
> From: Laszlo Ersek
> Sent: Tuesday, May 23, 2023 6:07 PM
> To: Gerd Hoffmann ; devel@edk2.groups.io
> Cc: Oliver Steffen ; Ard Biesheuvel
> ; Pawel Polawski ; Ni, Ray
> ; Yao, Jiewen ; Justen, Jordan L
>
> Subject: Re: [PATCH 1/1] OvmfPkg/Platf
On 5/23/23 10:25, Gerd Hoffmann wrote:
> Not needed any more, SMM + 64-bit PEI + S3 suspend works now.
>
> Fixed by commits:
> - 8bd2028f9ac3 ("MdeModulePkg: Supporting S3 in 64bit PEI")
> - 6acf72901a2e ("UefiCpuPkg: Supporting S3 in 64bit PEI")
> See also https://bugzilla.tianocore.org/show_bu
Hello,
Does PciHostBridge driver support dynamic pcie bus limit assignement?
For example, Xeon chip supports allocating pci bus range dynamically.
So, on a dedicated motherboard, during BIOS Post, user could change every cpu
socket's bus limit assignment dynamically ,
and so user could influene
This patch series looks good to me.
Reviewed-by: Nhi Pham
Thanks,
Nhi
On 5/16/2023 2:08 PM, Minh Nguyen wrote:
These patches help to fix an issue in SmbiosMiscDxe and remove redundant asign
for SmbiosHandle.
Minh Nguyen (2):
ArmPkg/SmbiosMiscDxe: Fix procedure to get handle of SMBIOS re
Hi Kun,
I've updated my answers in your original mail.
Thanks,
Dun
-Original Message-
From: Kun Qin
Sent: Saturday, May 20, 2023 10:00 AM
To: devel@edk2.groups.io; Tan, Dun
Cc: Dong, Eric ; Ni, Ray ; Kumar, Rahul
R ; Gerd Hoffmann
Subject: Re: [edk2-devel] [Patch V4 07/15] UefiCpuPk
(cc Rebecca)
On Tue, 23 May 2023 at 10:26, Gerd Hoffmann wrote:
>
> Not needed any more, SMM + 64-bit PEI + S3 suspend works now.
>
> Fixed by commits:
> - 8bd2028f9ac3 ("MdeModulePkg: Supporting S3 in 64bit PEI")
> - 6acf72901a2e ("UefiCpuPkg: Supporting S3 in 64bit PEI")
> See also https://bu
On Tue, 23 May 2023 at 10:50, Gerd Hoffmann wrote:
>
> Hi,
>
> > > Works (test patch below for reference).
> >
> > Excellent, thanks for confirming.
> >
> > So I think we should add this for all Clang configurations that enable
> > PIE codegen. We don't support GCC < 5 anyway so this gives us un
Hi,
> > Works (test patch below for reference).
>
> Excellent, thanks for confirming.
>
> So I think we should add this for all Clang configurations that enable
> PIE codegen. We don't support GCC < 5 anyway so this gives us uniform
> behavior for all ELF based toolchains used for x86.
Which
Not needed any more, SMM + 64-bit PEI + S3 suspend works now.
Fixed by commits:
- 8bd2028f9ac3 ("MdeModulePkg: Supporting S3 in 64bit PEI")
- 6acf72901a2e ("UefiCpuPkg: Supporting S3 in 64bit PEI")
See also https://bugzilla.tianocore.org/show_bug.cgi?id=4195
Signed-off-by: Gerd Hoffmann
---
O
> As long as edk2 (core modules) will continue supporting IA32X64 firmware
> platforms, I think keeping OVMF IA32X64 is useful, minimally as a test
> bed for those core modules / PCDs / boot paths. If it becomes difficult
> / costly to maintain OVMF IA32X64, then removing it might make sense at
> s
On Tue, 23 May 2023 at 10:05, Gerd Hoffmann wrote:
>
> Hi,
>
> > >> Before we enabled SMM for OVMF, we had never really used IA32X64 OVMF --
> > >> SMM-less ACPI S3 resume had just worked fine with X64-only OVMF. IA32X64
> > >> only proved a great platform option to fall back to, when we realize
MSFT:*_*_*_CC_FLAGS = /Od will disable build optimization.
Signed-off-by: Sheng Wei
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Jenny Huang
Cc: Robert Kowalewski
---
.../VTd/IntelVTdDmarPei/IntelVTdDmar.c| 43 +--
1 file changed, 31 insertions(+), 12 deletions(-)
diff --g
Hi,
> >> Before we enabled SMM for OVMF, we had never really used IA32X64 OVMF --
> >> SMM-less ACPI S3 resume had just worked fine with X64-only OVMF. IA32X64
> >> only proved a great platform option to fall back to, when we realized
> >> that on X64 OVMF, ACPI S3 resume wouldn't just seamlessl
On Tue, 23 May 2023 at 09:34, Laszlo Ersek wrote:
>
> On 5/23/23 07:39, Ni, Ray wrote:
> >
> >
> >> -Original Message-
> >> From: Laszlo Ersek
> >> Sent: Tuesday, May 23, 2023 1:31 PM
> >> To: Ard Biesheuvel ; edk2-devel-groups-io
> >> ; Ni, Ray ; Yao, Jiewen
> >> ; Gerd Hoffmann ; Taylor
On 5/23/23 07:39, Ni, Ray wrote:
>
>
>> -Original Message-
>> From: Laszlo Ersek
>> Sent: Tuesday, May 23, 2023 1:31 PM
>> To: Ard Biesheuvel ; edk2-devel-groups-io
>> ; Ni, Ray ; Yao, Jiewen
>> ; Gerd Hoffmann ; Taylor Beebe
>> ; Oliver Smith-Denny
>> Subject: Re: managing memory attri
On Mon, 22 May 2023 at 16:31, Gerd Hoffmann wrote:
>
> Hi,
>
> > > Recent clang does have a '-fdirect-access-external-data' switch which
> > > should suppress these references, maybe in combination with
> > > -fvisibility=hidden?
> >
> > I'll try that.
>
> Works (test patch below for reference).
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