Add EFIAPI to the implementations of:
BdsBeforeConsoleAfterTrustedConsoleCallback
BdsBeforeConsoleBeforeEndOfDxeGuidCallback
BdsAfterConsoleReadyBeforeBootOptionCallback
This makes them match the prototypes, and avoids an -Wlto-type-mismatch
warning.
Signed-off-by: Rebecca Cran
---
Platform/In
The following include files appear to be unused, since the build system
uses the corresponding files under WhiskeylakeOpenBoardPkg/Include
instead:
WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPlatformHookLib.h
WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPlatformLib.h
WhiskeylakeOpe
Fix the ALIGN16 macro in Platform/Intel/WhiskeylakeOpenBoardPkg to use
ADDRESS_IS_ALIGNED from MdePkg/Include/Base.h, and delete include files
which appear to be unused.
Testing:
./build_bios.py -p UpXtreme {-d,-r,-tr,-rp,--capsule,--performance,--fsp}
Rebecca Cran (2):
Platform/Intel/Whiskeyl
The IS_ALIGNED macro defined in PlatformBoardConfig.h conflicts with the
definition from MdePkg/Include/Base.h. Delete it, and switch to
ADDRESS_IS_ALIGNED.
Signed-off-by: Rebecca Cran
---
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformBoardConfig.h
| 3 +--
1 file chan
[AMD Official Use Only - General]
Reviewed-by: Abner Chang
> -Original Message-
> From: Nickle Wang
> Sent: Monday, May 15, 2023 12:25 PM
> To: devel@edk2.groups.io
> Cc: Chang, Abner ; Igor Kulchytskyy
>
> Subject: [PATCH] RedfishPkg/RedfishPlatformConfigDxe: Fix string assert
> issue
When calling SetValue() with string type input, there is
assertion of providing zero string ID to HII string function.
Fix this issue by creating string ID for input string buffer.
Fix Unicode and Ascii code convert issue together.
Add text op-code support
Signed-off-by: Nickle Wang
Cc: Abner Cha
[AMD Official Use Only - General]
Hi Nickle,
I read though this patch and was confused by function naming and the function
description in the function header. I think we have to revise it and make the
description of functionality clear for user to follow.
I apologize if we ever discussed this
Hi Liming,
These typos are found during reviews, sync with open source and other debug.
Just kept running list and then a simple search and replace in repo.
I have fix for other packages too, just starting with MdePkg to get some
feedback on size of patch (number of files etc)
I am using VS Co
UefiPayloadPkg looks good for me. But maybe need to wait hard freeze unlock
first. Give my RB.
Reviewed-by: Gua Guo
-Original Message-
From: Wu, Jiaxin
Sent: Monday, May 15, 2023 10:16 AM
To: devel@edk2.groups.io
Cc: Dong, Guo ; Rhodes, Sean ; Lu,
James ; Guo, Gua ; Ni, Ray
; Zeng,
Add CpuPageTableLib required by SecCore & CpuMpPei in UefiPayloadPkg.
Cc: Guo Dong
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Cc: Ray Ni
Cc: Zeng Star
Signed-off-by: Jiaxin Wu
---
UefiPayloadPkg/UefiPayloadPkg.dsc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/UefiPayloa
Add CpuPageTableLib required by SecCore & CpuMpPei in OvmfPkg.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Ray Ni
Cc: Zeng Star
Signed-off-by: Jiaxin Wu
---
OvmfPkg/AmdSev/AmdSevX64.dsc | 2 +-
OvmfPkg/CloudHv/CloudHvX64.dsc | 2 +-
OvmfPkg/IntelTdx/Inte
System paging 5 level enabled or not can be checked via CR4.LA57, system
preferred Page table Level (PcdUse5LevelPageTable) must align with previous
level for 64bit long mode.
This patch is to do the wise check:
If cpu has already run in 64bit long mode PEI, Page table Level in DXE
must align with
Some security features depend on the page table enabling. So, This
patch is to enable paging if it is not enabled (32bit mode)"
Cc: Eric Dong
Cc: Ray Ni
Cc: Zeng Star
Cc: Gerd Hoffmann
Cc: Rahul Kumar
Signed-off-by: Jiaxin Wu
---
UefiCpuPkg/CpuMpPei/CpuMpPei.h | 1 +
UefiCpuPkg/CpuMpPei
Background:
For arch X64, system will enable the page table in SPI to cover 0-512G
range via CR4.PAE & MSR.LME & CR0.PG & CR3 setting (see ResetVector code).
Existing code doesn't cover the higher address access above 512G before
memory-discovered callback. That will be potential problem if system
For arch X64, system will enable the page table in SPI to cover 0-512G
range via CR4.PAE & MSR.LME & CR0.PG & CR3 setting. Existing code doesn't
cover the higher address access above 512G before memory-discovered
callback. This series patches provide the solution to enable paging from
temporary RAM
[AMD Official Use Only - General]
Typo fixed, I will do the spell check for the new submitted patch.
Thank you.
Abner
> -Original Message-
> From: Tinh Nguyen
> Sent: Monday, May 15, 2023 1:24 AM
> To: Chang, Abner ; devel@edk2.groups.io
> Cc: Isaac Oram ; Attar, AbdulLateef (Abdul Latee
[AMD Official Use Only - General]
Thanks Tinh, that typo is corrected. Just I am not going to send another
version of patch set for this change for review.
Abner
> -Original Message-
> From: Tinh Nguyen
> Sent: Monday, May 15, 2023 12:47 AM
> To: Chang, Abner ; devel@edk2.groups.io
> Cc
Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create
5 level page table.
If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created
at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if
5level paging is supported, use PML5Table, otherwise, use PML4Table.
If macro USE_
From: "Liu, Zhiguang"
In ResetVector, if create page table, its highest address is fixed
because after page table, code layout is fixed(4K for normal code,
and another 4K only contains reset vector code).
Today's implementation organizes the page table as following if 1G
page table is used:
4G-
From: "Liu, Zhiguang"
Combine PageTables1G.asm and PageTables2M.asm to reuse code.
Cc: Eric Dong
Reviewed-by: Ray Ni
Cc: Rahul Kumar
Tested-by: Gerd Hoffmann
Acked-by: Gerd Hoffmann
Cc: Debkumar De
Cc: Catharine West
Signed-off-by: Zhiguang Liu
---
UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
From: "Liu, Zhiguang"
Currently, page table creation has many hard-code values about the
offset to the start of page table. To simplify it, add Labels such
as Pml4, Pdp and Pd, so that we can remove many hard-code values
Cc: Eric Dong
Reviewed-by: Ray Ni
Cc: Rahul Kumar
Tested-by: Gerd Hoffma
From: "Liu, Zhiguang"
This patch only renames macro, with no code logic impacted.
Two purpose to rename macro:
1. Align some macro name in PageTables1G.asm and PageTables2M.asm, so
that these two files can be easily combined later.
2. Some Macro names such as PDP are not accurate, since 4 level p
This patch set simplify the page table creation code, remove some
hard-code, combine files and support 5 Level paging.
V4:
Refine comments and update below macro names:
PG_NLE -> PAGE_NLE
PTE_2MB -> PDE_2MB
PDP_1G -> PDPTE_1GB
PAGE_BLP_ATTR -> PAGE_BLE_ATTR
No code logic impact
V5:
Update below m
Giri:
How do you find these typos? Which tool do you use to scan the code?
Thanks
Liming
> -邮件原件-
> 发件人: Giri Mudusuru
> 发送时间: 2023年5月12日 18:25
> 收件人: devel@edk2.groups.io
> 抄送: Giri Mudusuru ; Michael D Kinney
> ; Liming Gao ;
> Zhiguang Liu ; Andrew Fish
> 主题: [PATCH] MdePkg Include:
Guo:
This is a bug fix. I think it is OK to merge for this stable tag.
Thanks
Liming
> -邮件原件-
> 发件人: devel@edk2.groups.io 代表 Guo Dong
> 发送时间: 2023年5月13日 7:40
> 收件人: devel@edk2.groups.io; Gao, Liming
> 抄送: Ni, Ray ; Rhodes, Sean ;
> Lu, James ; Guo, Gua
> 主题: Re: [edk2-devel][PATCH V2
Chasel:
I just merge it.
Thanks
Liming
> -邮件原件-
> 发件人: devel@edk2.groups.io 代表 Chiu, Chasel
> 发送时间: 2023年5月12日 15:15
> 收件人: devel@edk2.groups.io; Chiu, Chasel ; Gao,
> Liming ; Guo, Gua
> 抄送: 'Andrew Fish' ; 'Leif Lindholm'
> ; Kinney, Michael D
>
> 主题: Re: [edk2-devel] [PATCH v1 0/1
Ard:
I am OK.
Thanks
Liming
> -邮件原件-
> 发件人: devel@edk2.groups.io 代表 Ard
> Biesheuvel
> 发送时间: 2023年5月12日 14:40
> 收件人: devel@edk2.groups.io; kra...@redhat.com
> 抄送: Rebecca Cran ; Liming Gao
>
> 主题: Re: [edk2-devel] [PATCH] BaseTools/tools_def: Disable overzealous
> unused variable warn
*Reminder: Tools, CI, Code base construction meeting series*
*When:*
Monday, May 15, 2023
4:30pm to 5:30pm
(UTC-07:00) America/Los Angeles
*Where:*
https://github.com/tianocore/edk2/discussions/2614
View Event ( https://edk2.groups.io/g/devel/viewevent?eventid=1890534 )
*Description:*
TianoCor
Reviewed-by: Tinh Nguyen
Regards,
- Tinh
On 12/05/2023 16:58, Chang, Abner via groups.io wrote:
From: Abner Chang
Add IpmiBmcElog to ManageabilityPkg.
Signed-off-by: Abner Chang
Cc: Isaac Oram
Cc: Abdul Lateef Attar
Cc: Nickle Wang
---
Features/ManageabilityPkg/ManageabilityPkg.dec
There is a minor typo below
Reviewed-by: Tinh Nguyen
Regards,
- Tinh
On 12/05/2023 16:58, abner.ch...@amd.com wrote:
From: Abner Chang
IpmiBmcElog is cloned from
edk2-platforms/Features/Intel/OutOfBandManagement/
IpmiFeaturePkg/BmcElog in order to consolidate
edk2 system manageability su
Reviewed-by: Tinh Nguyen
Regards,
- Tinh
On 12/05/2023 11:06, Chang, Abner via groups.io wrote:
From: Abner Chang
Add IpmiOsWdt to ManageabilityPkg.
Signed-off-by: Abner Chang
Cc: Isaac Oram
Cc: Abdul Lateef Attar
Cc: Nickle Wang
---
Features/ManageabilityPkg/ManageabilityPkg.dec
Reviewed-by: Tinh Nguyen
Regards,
- Tinh
On 12/05/2023 11:06, Chang, Abner via groups.io wrote:
From: Abner Chang
IpmiOsWdt is cloned from
edk2-platforms/Features/Intel/OutOfBandManagement/
IpmiFeaturePkg/OsWdt in order to consolidate
edk2 system manageability support in one place.
Uncustif
Reviewed-by: Tinh Nguyen
There is a minor typo that I commented on below.
On 13/05/2023 19:33, abner.ch...@amd.com wrote:
From: Abner Chang
IpmiFrb is cloned from
edk2-platforms/Features/Intel/OutOfBandManagement/
IpmiFeaturePkg/Frb in order to consolidate
edk2 system manageability support
[AMD Official Use Only - General]
Reviewed-by: Abner Chang
> -Original Message-
> From: Nickle Wang
> Sent: Friday, May 12, 2023 2:25 PM
> To: devel@edk2.groups.io
> Cc: Chang, Abner ; Igor Kulchytskyy
>
> Subject: [edk2-redfish-client][PATCH] RedfishClientPkg/ConverterLib: Fix
> empty
Hi Ray, Zhichao
Could you please help to review this change?
Thanks,
Simon
Could you please help to review this change?
Thanks,
Simon
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