On Thu, Feb 03, 2022 at 09:56:25PM +0100, Nicolas Ojeda Leon wrote:
> Consume the host-provided specification of PCI host bridges if
> available. Using the DxeHardwareInfoLib, populate a list of
> hardware descriptors based on the content of the "hardware-info"
> fw-cfg file, if provided. In the af
Hi Isaac,
This change looks good to me.
Reviewed-by: Daocheng Bu
Thanks,
Amos
Silicon IP Firmware Engineering
UEFI FW, IAFW, System Firmware or Host Firmware is more generic & accurate
It's not BIOS anymore!
-Original Message-
From: Oram, Isaac W
Sent: Friday, February 4, 2022
Extend the PCI BAR placement logic in order to consider pre-populated
resources first, if indicated by the Pcd token for such purpose.
The PCI_BAR type is augmented by one field for mapping the absolute
address of prepopulated BARs into a root bridge relative offset.
As part of the CreateResourceM
Enhance the PCI Resource Allocation services to include a new state in
which only the base address of each root bridge is set. This new, partial
state is used in conjunction with GetProposedResources to retrieve the
Base Addresses of the resources before the allocation takes place, and
is reached o
Create a new PCD boolean token in MdeModulePkg for global use.
We use this token to indicate if the configuration, parsed from
fw-cfg, requires pre-populated BARs to be preserved.
During creation of root bridges configurations, the flag is set
according to the "pre-populated-bars" item in fw-cfg.
Consume the host-provided specification of PCI host bridges if
available. Using the DxeHardwareInfoLib, populate a list of
hardware descriptors based on the content of the "hardware-info"
fw-cfg file, if provided. In the affirmative case, use the
resources and attributes specified by the hypervisor
Read the "hardware-info" item from fw-cfg to extract specifications
of PCI host bridges and analyze the 64-bit apertures of them to
find out the highest 64-bit MMIO address required which determines
the address space required by the guest, and, consequently, the
FirstNonAddress used to calculate si
Define the HardwareInfoLib API and create the PeiHardwareInfoLib
which implements it, specifically for Pei usage, supporting
only static accesses to parse data directly from a fw-cfg file.
All list-like APIs are implemented as unsupported and only a
fw-cfg wrapper to read hardware info elements is
Increased control is provided in Ovmf platforms to define and configure
the specifications of multiple PCI host bridges in the hypervisor. The
host propagates this information to the guest, initially through fw-cfg
interface.
In some AWS EC2 platforms, we expose a PCI topology including several
ro
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3794
This change introduces a new error code definitions under Host Software
class.
The new error code definition will cover system reboot events under the
conditions of fragmented memory map from one boot to another.
These error codes could pr
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3794
This patch series is a rebase of previous submission:
https://edk2.groups.io/g/devel/message/85335
In current Status Codes definitions of PI spec v1.7 errata, there are a
few instances where the software could trigger system reboots while t
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3794
This change includes specification update markdown file that describes
the proposed PI Specification v1.7 Errata A in detail and potential
impact to the existing codebase.
Cc: Andrew Fish
Cc: Leif Lindholm
Cc: Michael D Kinney
Cc: Liming
Add a vendor reserved range to avoid collisions with Intel reference
board ID future use, if any.
Cc: Nate DeSimone
Cc: Chasel Chiu
Signed-off-by: Isaac Oram
---
Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.c |
3 +-
Platform/Intel/WhitleyOpenBoardPkg/Readme.md
This series adds a template for board porting and the infrastruture to support.
V2:
1/2: No change
2/2: Updated Readme.md per feedback, elaborating on naming and fixing
formatting issues.
V1:
The WhitleyOpenBoardPkg/Readme.md documents the step by step instructions to
create a new board tip t
The Neoverse reference design platforms support AArch32 execution
state only at the EL0 exception level. So allow only the AArch64
builds for these platforms.
Signed-off-by: Nishant Sharma
Reported-by: Rebecca Cran
---
Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc | 4 ++--
Platform/ARM/SgiPkg/
Hi Andrew,
I think it would be useful to define a few macros for PANIC() conditions that
would make it easy to convert an existing ASSERT() condition that is really
a PANIC() condition by simply using a different macro name. One attribute of
this macro (unlike DEBUG() and ASSERT() macros) is that
Provide a build option to use [Esc] instead of [F2] for devices
such as Chromebooks that don't have F-keys.
Signed-off-by: Sean Rhodes
---
.../PlatformBootManager.c | 44 +--
.../PlatformBootManagerLib.inf| 1 +
UefiPayloadPkg/UefiPayloadPkg.d
Hi All,
We are going to skip the IORT Rev E.b and E.c. I will be submitting a new patch
series, so please ignore this series.
Regards,
Sami Mujawar
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View/Reply Online (#86367): https://edk2.groups.io/g/devel/
Hi All,
We are going to skip the IORT Rev E.b and E.c. I will be submitting a new patch
series, so please ignore this series.
Regards,
Sami Mujawar
On 03/02/2022, 15:24, "devel@edk2.groups.io on behalf of Rebecca Cran via
groups.io"
wrote:
Reviewed-by: Rebecca Cran
On 11/10/21
Reviewed-by: Rebecca Cran
On 11/10/21 03:55, Sami Mujawar wrote:
Bugzilla: 3458 - Add support IORT Rev E.b specification updates
(https://bugzilla.tianocore.org/show_bug.cgi?id=3458)
The IO Remapping Table, Platform Design Document, Revision E.b,
Feb 2021 (https://developer.arm.com
On Thu, 3 Feb 2022 at 11:25, Nishant Sharma wrote:
>
> The Neoverse reference design platforms support AArch32 execution
> state only at the EL0 exception level. So allow only the AArch64
> builds for these platforms.
>
> Signed-off-by: Nishant Sharma
> Reported-by: Rebecca Cran
Reviewed-by
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