Reviewed-by: Star Zeng
-Original Message-
From: Kinney, Michael D
Sent: Saturday, January 22, 2022 9:41 AM
To: devel@edk2.groups.io
Cc: Wu, Hao A ; Ni, Ray ; Zeng, Star
Subject: [Patch 1/1] MdeModulePkg/Bus/Pci/PciBusDxe: Support platform PCI ROM
override
REF: https://bugzilla.tiano
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Intel's Trust Domain Extensions (Intel TDX) refers to an Intel technology
that extends Virtual Machines Extensions (VMX) and Multi-Key Total Memory
Encryption (MKTME) with a new kind of virutal machines guest called a
Trust Domain (TD). A TD
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
The entrypoint of DxeAcpiTimerLib checks HostBridgeDevId by reading
PcdOvmfHostBridgePciDevId. If the DevId is not set, ASSERT is
triggered. Normally this DevId is set in PlatformPei which is executed
in PEI phase. But Tdvf Config-B skips PE
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
TDX_PEI_LESS_BOOT indicates the boot without PEI phase. In this case
settings in EFI_HOB_PLATFORM_INFO should be set to its according PCDs.
TdxDxe driver is workable for both Legacy guest and Tdx guest. It is
because for Legacy guest (in PEI
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
OvmfPkg/IntelTdx/Sec is a simplied version of OvmfPkg/Sec. There
are below differences between these 2 Sec
- IntelTdx/Sec only supports Legacy guest and Tdx guest.
- IntelTdx/Sec calls TdxStartup () to jump from SEC to DXE directly.
- Int
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
TdxStarupLib provides a function (TdxStartup ()) which brings up both
Legacy and Tdx guest from SEC phase to DXE phase. PEI phase is skipped
so that the attack surfaces are reduced as much as possible.
TdxStartup() does below tasks:
1. Cont
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
This patch-sets is to bring up Legacy guest and Tdx guest without
PEI phase. So platform initialization has to be done in SEC phase.
It is similar with the work of OvmfPkg/PlatformPei. In
OvmfPkg/PlatformPei some PCDs are set during platform
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
This library sets / gets the Hob list pointer in TDX_WORK_AREA.
This is because it is designed to be used in SEC where the value of
global variable cannot be saved, so the Hob list pointer is saved
in TDX_WORK_AREA.
Cc: Michael D Kinney
Cc
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Add PcdTdxWorkAreaBase to indicate the area of memory where
the TDX work area block lives.
Cc: Ard Biesheuvel
Cc: Jordan Justen
Cc: Brijesh Singh
Cc: Erdem Aktas
Cc: James Bottomley
Cc: Jiewen Yao
Cc: Tom Lendacky
Cc: Gerd Hoffmann
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Add the TDX work area definition.
Cc: Michael D Kinney
Cc: Brijesh Singh
Cc: Erdem Aktas
Cc: James Bottomley
Cc: Jiewen Yao
Cc: Tom Lendacky
Cc: Gerd Hoffmann
Signed-off-by: Min Xu
---
OvmfPkg/Include/WorkArea.h | 15 ++
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
CompressedDataLength is declared as UINTN which is UINT64 in X64 arch.
But the second parameter of UefiDecompressGetInfo() is declared as
UINT32. So a build error is triggered. To declare CompressedDataLength
as UINT32 to fix the build error
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Intel's Trust Domain Extensions (Intel TDX) refers to an Intel technology
that extends Virtual Machines Extensions (VMX) and Multi-Key Total Memory
Encryption (MKTME) with a new kind of virutal machines guest called a
Trust Domain (TD). A TD
Reviewed-by: Ray Ni
-Original Message-
From: Liu, Zhiguang
Sent: Wednesday, January 19, 2022 5:17 PM
To: devel@edk2.groups.io
Cc: Dong, Guo ; Ni, Ray ; Ma, Maurice
; You, Benjamin
Subject: [PATCH] UefiPayloadPkg: Use BaseCpuTimerLib for Universal Payload by
default
Current, a macro
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This series adds a template for board porting and the infrastruture to support.
V2:
Updated Readme.md board naming convention discussion per feedback.
V1:
The WhitleyOpenBoardPkg/Readme.md documents the step by step instructions to
create a new board tip that builds.
The BoardPortTemplate contai
Liming:
> -Original Message-
> From: gaoliming
> Sent: Friday, January 21, 2022 1:16 PM
> To: Zhang, Di ; Chen, Lin Z ;
> devel@edk2.groups.io; Huang, Long1 ; Kinney,
> Michael D
> Cc: Bi, Dandan ; Feng, Bob C ;
> Li, Zhuangzhi
> Subject: 回复: [edk2-devel] [PATCH] MdeModulePkg/HiiDataba
When creating FIT table, if a IBB FV (e.g. Security FV) is blow ACM FV
( e.g. Firmware Binaries FV), but the size of IBB FV is smaller than
ACM FV, it will cause overflow issue, unexpected split will happen.
Added a statement checking to avoid this issue.
Cc: Bob Feng
Cc: Liming Gao
Cc: Yuwei Ch
Mike,
Just my two cents:
I think adding intrinsic libraries is a mixed bag, for the following
reasons:
1) The intrinsic libraries are completely internal to the compilers.
Breaking down that toolchain/code barrier is not a good idea if we want the
project to compile using a good variety of compi
Merged as 805059812997..239181acdd45
Regards,
Sami Mujawar
From: devel@edk2.groups.io on behalf of Sami Mujawar via
groups.io
Date: Monday, 24 January 2022 at 18:16
To: Khasim Mohammed , devel@edk2.groups.io
Cc: nd , Pierre Gondois , Khasim Mohammed
Subject: Re: [edk2-devel] [PATCH v7 0/6
Hi Khasim,
Thank you for splitting the patches.
For this series,
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
From: Khasim Mohammed
Date: Monday, 24 January 2022 at 15:56
To: devel@edk2.groups.io
Cc: nd , Sami Mujawar , Pierre Gondois
, Khasim Mohammed
Subject: [PATCH v7 0/6] Enable C
Hi Kilian,
I am in favor of an intrinsic lib to improve the EDK II development environment.
This has already been done for ARM compilers. The solution should mirror that
approach.
It would be best if we had source code (either in the edk2 repo or through a
submodule) for
the required intrinsi
The 64-bit integer math intrinsics and other intrinsic
problems could be solved easily for ever:
1. Putting all .OBJ files together from LIBCMT.H or INT64.LIB (for ll*.obj
and ull*.obj only)
ltod3.obj
ftol2.obj
lldiv.obj
lldvrm.obj
llmul.obj
llrem.obj
llshl.obj
llshr.obj
ulldiv.obj
Update N1Sdp Platform dsc to use PciSegmentLib instead of PciExpressLib.
Signed-off-by: Khasim Syed Mohammed
---
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
b/Platform/ARM/N1Sdp/N1SdpPlatform.ds
The patch removes PciExpressLib implementation for N1Sdp as:
a) The PciSegmentLib implementation for N1Sdp makes MmioRead() calls
instead of PciRead() which makes the PciExpressLib redundant.
b) Since N1Sdp requires multiple segments to be supported, PciExpressLib
and PciLib cannot
This patch enables CCIX root complex support by updating
the root complex node info in PciHostBridge library.
Signed-off-by: Khasim Syed Mohammed
---
.../PciHostBridgeLib/PciHostBridgeLib.c | 71 +--
.../PciHostBridgeLib/PciHostBridgeLib.inf | 11 ++-
2 files changed, 7
PCD entries are updated to add support for multiple PCI root ports.
Signed-off-by: Khasim Syed Mohammed
---
.../AslTables/SsdtPci.asl | 8 +++
.../AslTables/SsdtRemotePci.asl | 4 ++--
.../ConfigurationManager.c| 24 +--
The BasePCISegment Library in MdePkg doesn't allow configuring
multiple segments required for PCIe and CCIX root port
enumeration. Therefore, a custom PCI Segment library is adapted
from SynQuacerPciSegmentLib and ported for N1Sdp.
In addition to this, the hardware has few other limitations which
PCD entries are updated to remove the hardcoded assignments and to
add support for multiple PCI root ports.
Signed-off-by: Khasim Syed Mohammed
---
.../Library/PlatformLib/PlatformLib.inf | 1 +
.../Library/PlatformLib/PlatformLibMem.c | 4 +-
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc
The patch series removes PciExpressLib and enables CCIX port
as PCIe root on N1SDP.
V7:
- Spit the patches to separate Platform and Silicon specific files
V6:
- Sort PCDs in alphabetical order
- Replace ASSERT calls with a if condition to capture the failure
V5:
- Split the CCIX patch, separate
Remove BaseCachingPciExpressLib library from ArmVirtPkg and use the one under
OvmfPkg instead.
BaseCachingPciExpressLib is cloned to under OvmfPkg, with this change the RISC-V
Virt platform can leverage the same library.
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
Cc: Ard Biesh
Clone BaseCachingPciExpressLib library from ArmVirtPkg to under OvmfPkg.
RISC-V Virt platform can leverage the same library to access PCI Express
registers through PCI Express base address set in PcdPciExpressBaseAddress
and cached in a global variable.
Signed-off-by: Abner Chang
Cc: Daniel Schae
Clone BaseCachingPciExpressLib library from ArmVirtPkg to under OvmfPkg.
RISC-V Virt platform can leverage the same library to access PCI Express
registers through PCI Express base address set in PcdPciExpressBaseAddress
and cached in a global variable. Also remove the one under ArmVirtPkg.
Signed
Pushed as 8eb3b2f8be26..805059812997
Thanks.
Regards,
Sami Mujawar
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Hi Khasim,
Thank you for the updated patch series.
These changes look good to me.
For this series,
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 22/01/2022 03:26 PM, Khasim Syed Mohammed wrote:
The patch series removes PciExpressLib and enables CCIX port
as PCIe root on N1SDP.
V6:
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