On 03/02/20 18:12, Laszlo Ersek wrote:
> On 03/02/20 08:29, Ard Biesheuvel wrote:
>> Implement QemuLoadImageLib, and make it load the image provided by the
>> QEMU_EFI_LOADER_FS_MEDIA_GUID/kernel device path that we implemented
>> in a preceding patch in a separate DXE driver, using only the standa
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
A hypervisor is not allowed to update an SEV-ES guest's register state,
so when booting an SEV-ES guest AP, the hypervisor is not allowed to
set the RIP to the guest requested value. Instead an SEV-ES AP must be
re-directed from within the gu
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
After having transitioned from UEFI to the OS, the OS will need to boot
the APs. For an SEV-ES guest, the APs will have been parked by UEFI using
GHCB pages allocated by UEFI. The hypervisor will write to the GHCB
SW_EXITINFO2 field of the GH
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Before UEFI transfers control to the OS, it must park the AP. This is
done using the AsmRelocateApLoop function to transition into 32-bit
non-paging mode. For an SEV-ES guest, a few additional things must be
done:
- AsmRelocateApLoop must b
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
A GHCB page is needed during the Sec phase, so this new page must be
created. Since the #VC exception handler routines assume that a per-CPU
variable area is immediately after the GHCB, this per-CPU variable area
must also be created. Since t
On 3/2/20 5:06 PM, Tom Lendacky wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> A GHCB page is needed during the Sec phase, so this new page must be
> created. Since the #VC exception handler routines assume that a per-CPU
> variable area is immediately after the GHCB, this pe
Thanks for the feedback. I will send V3 patch.
I also make that correction in closed source.
-Original Message-
From: Chiu, Chasel
Sent: Monday, March 2, 2020 7:59 PM
To: Shindo, Miki ; devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Desimone, Nathaniel L
; Agyeman, Prince
Subject: R
Hi Shindo,
Please see my comments below inline.
With that updated: Reviewed-by: Chasel Chiu
Thanks,
Chasel
> -Original Message-
> From: Shindo, Miki
> Sent: Tuesday, March 3, 2020 9:50 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
*Reminder:* TianoCore Community Meeting - APAC/NAMO
*When:* Thursday, 5 March 2020, 7:30pm to 8:30pm, (GMT-08:00) America/Los
Angeles
*Where:* https://bluejeans.com/889357567?src=join_info
View Event ( https://edk2.groups.io/g/devel/viewevent?eventid=621372 )
*Organizer:* Brian Richardson bria
REF : https://bugzilla.tianocore.org/show_bug.cgi?id=2542
ReportPreMemFv () has redundant calls to install Fsp FVs.
FSP-M, S, U FVs do not need to be installed
when Fsp Wrapper Boot Mode is disabled.
Signed-off-by: Miki Shindo
Cc: Sai Chaganty
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Prince Agye
Hi, all
Thanks for your patience. Based on the discussion
https://edk2.groups.io/g/devel/message/55092, edk2-stable202002 tag will be
created on Mar 4th (UTC ? 8 00:00:00). Once the tag is created, I will send the
announcement.
Thanks
Liming
-Original Message-
From: annou...@edk2.gro
Hi Laszlo,
Reviewed-by: Eric Dong
Thanks,
Eric
> -Original Message-
> From: Laszlo Ersek [mailto:ler...@redhat.com]
> Sent: Thursday, February 27, 2020 6:12 AM
> To: edk2-devel-groups-io
> Cc: Ard Biesheuvel ; Dong, Eric
> ; Wu, Hao A ; Igor Mammedov
> ; Wang, Jian J ; Yao,
> Jiewen ; J
Reviewed-by: jiewen@intel.com
From: De Leon Vazquez, Lorena R
Sent: Tuesday, March 3, 2020 7:04 AM
To: devel@edk2.groups.io
Cc: Yao, Jiewen ; Kinney, Michael D
Subject: [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix
Looks like Addresswidth is BIT wise values. Right now the
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
The flash detection routine will attempt to determine how the flash
device behaves (e.g. ROM, RAM, Flash). But when SEV-ES is enabled and
the flash device behaves as a ROM device (meaning it is marked read-only
by the hypervisor), this check
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Typically, an AP is booted using the INIT-SIPI-SIPI sequence. This
sequence is intercepted by the hypervisor, which sets the AP's registers
to the values requested by the sequence. At that point, the hypervisor can
start the AP, which will th
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Currently, the OVMF code relies on the hypervisor to enable the cache
support on the processor in order to improve the boot speed. However,
with SEV-ES, the hypervisor is not allowed to change the CR0 register
to enable caching.
Update the O
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
During BSP startup, the reset vector code will issue a CPUID instruction
while in 32-bit mode. When running as an SEV-ES guest, this will trigger
a #VC exception.
Add exception handling support to the early reset vector code to catch
these e
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
A hypervisor is not allowed to update an SEV-ES guests register state,
so when booting an SEV-ES guest AP, the hypervisor is not allowed to
set the RIP to the guest requested value. Instead, an SEV-ES AP must be
transition from 64-bit long mo
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Create an SEV-ES workarea PCD. This PCD will be used for BSP communication
during SEC and for AP startup during PEI and DXE phases, the latter is the
reason for creating it in the UefiCpuPkg.
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Sign
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
When starting APs in an SMP configuration, the AP needs to know if it is
running as an SEV-ES guest in order to assign a GHCB page.
Add a field to the CPU_MP_DATA structure that will indicate if SEV-ES is
enabled. This new field is set durin
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
An SEV-ES guest will generate a #VC exception when it encounters a
non-automatic exit (NAE) event. It is expected that the #VC exception
handler will communicate with the hypervisor using the GHCB to handle
the NAE event.
NAE events can occu
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
The SEV support will clear the C-bit from non-RAM areas. The early GDT
lives in a non-RAM area, so when an exception occurs (like a #VC) the GDT
will be read as un-encrypted even though it is encrypted. This will result
in a failure to be ab
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Reserve a fixed area of memory for SEV-ES use and set a fixed PCD,
PcdSevEsWorkAreaBase, to this value.
This area will be used by SEV-ES support for two purposes:
1. Communicating the SEV-ES status during BSP boot to SEC:
Using a byte
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a RDTSCP intercept generates a #VC exception. VMGEXIT must be
used to allow the hypervisor to handle this intercept.
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Signed-off-by: Tom Lendacky
---
.../X64/ArchAMDSevVcHandler.c
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
VMGEXIT is a new instruction used for Hypervisor/Guest communication when
running as an SEV-ES guest. A VMGEXIT will cause an automatic exit (AE)
to occur, resulting in a #VMEXIT with an exit code value of 0x403.
Provide the necessary suppor
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Create a function that can be used to determine if the VM is running
as an SEV-ES guest.
Cc: Jordan Justen
Cc: Laszlo Ersek
Cc: Ard Biesheuvel
Reviewed-by: Laszlo Ersek
Signed-off-by: Tom Lendacky
---
OvmfPkg/Include/Library/MemEncrypt
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a IOIO_PROT intercept generates a #VC exception. VMGEXIT
must be used to allow the hypervisor to handle this intercept.
Add support to construct the required GHCB values to support a IOIO_PROT
NAE event. Parse the instruction
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
When SEV-ES is enabled, then SEV is also enabled. Add support to the SEV
initialization function to also check for SEV-ES being enabled, and if
enabled, set the SEV-ES enabled PCD (PcdSevEsIsEnabled).
Cc: Jordan Justen
Cc: Laszlo Ersek
Cc:
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a RDPMC intercept generates a #VC exception. VMGEXIT must be
used to allow the hypervisor to handle this intercept.
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Signed-off-by: Tom Lendacky
---
.../X64/ArchAMDSevVcHandler.c
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a MWAIT/MWAITX intercept generates a #VC exception.
VMGEXIT must be used to allow the hypervisor to handle this intercept.
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Signed-off-by: Tom Lendacky
---
.../X64/ArchAMDSevVcHandl
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a WBINVD intercept generates a #VC exception. VMGEXIT must be
used to allow the hypervisor to handle this intercept.
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Signed-off-by: Tom Lendacky
---
.../X64/ArchAMDSevVcHandler.c
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a MONITOR/MONITORX intercept generates a #VC exception.
VMGEXIT must be used to allow the hypervisor to handle this intercept.
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Signed-off-by: Tom Lendacky
---
.../X64/ArchAMDSevVcH
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a RDTSC intercept generates a #VC exception. VMGEXIT must be
used to allow the hypervisor to handle this intercept.
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Signed-off-by: Tom Lendacky
---
.../X64/ArchAMDSevVcHandler.c
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Various CpuExceptionHandlerLib libraries will updated to use the new
VmgExitLib library. To prevent any build breakage, update the
UefiPayloadPkg DSC files that use a form of the CpuExceptionHandlerLib
library to include the VmgExitLib librar
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Various CpuExceptionHandlerLib libraries will updated to use the new
VmgExitLib library. To prevent any build breakage, update the OvmfPkg
DSC files that use a form of the CpuExceptionHandlerLib library to
include the VmgExitLib library.
Cc:
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Add base support to handle #VC exceptions. This includes a stub routine
to invoke when a #VC exception occurs and special checks in the common
exception handlers to invoke the #VC exception handler routine.
Cc: Eric Dong
Cc: Ray Ni
Cc: La
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a DR7 read or write intercept generates a #VC exception.
The #VC handler must provide special support to the guest for this. On
a DR7 write, the #VC handler must cache the value and issue a VMGEXIT
to notify the hypervisor of th
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Protect the memory used by an SEV-ES guest when S3 is supported. This
includes the page table used to break down the 2MB page that contains
the GHCB so that it can be marked un-encrypted, as well as the GHCB
area.
Regarding the lifecycle of
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Allocate memory for the GHCB pages and the per-CPU variable pages during
SEV initialization for use during Pei and Dxe phases. The GHCB page(s)
must be shared pages, so clear the encryption mask from the current page
table entries. Upon succe
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a VMMCALL intercept generates a #VC exception. VMGEXIT must
be used to allow the hypervisor to handle this intercept.
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Signed-off-by: Tom Lendacky
---
.../X64/ArchAMDSevVcHandler.c
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a MSR_PROT intercept generates a #VC exception. VMGEXIT must
be used to allow the hypervisor to handle this intercept.
Add support to construct the required GHCB values to support an MSR_PROT
NAE event. Parse the instruction th
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a INVD intercept generates a #VC exception. VMGEXIT must be
used to allow the hypervisor to handle this intercept.
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Signed-off-by: Tom Lendacky
---
.../X64/ArchAMDSevVcHandler.c
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Add support to the #VC exception handler to handle string IO. This
requires expanding the IO instruction parsing to recognize string based
IO instructions as well as preparing an un-encrypted buffer to be used
to transfer (either to or from t
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
GHCB pages must be mapped as shared pages, so modify the process of
creating identity mapped pagetable entries so that GHCB entries are
created without the encryption bit set.
Cc: Jian J Wang
Cc: Hao A Wu
Cc: Dandan Bi
Cc: Liming Gao
Sig
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Three new dynamic PCDs are needed to support SEV-ES under OVMF:
- PcdSevEsIsEnabled: BOOLEAN value used to indicate if SEV-ES is enabled
- PcdGhcbBase: UINT64 value that is the base address of the GHCB
allocat
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a CPUID instruction requires the current value of the XCR0
register. In order to retrieve that value, the XGETBV instruction needs
to be executed.
Provide the necessary support to execute the XGETBV instruction.
Cc: Michael D
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
A GHCB page is needed during the Sec phase, so this new page must be
created. Since the #VC exception handler routines assume that a per-CPU
variable area is immediately after the GHCB, this per-CPU variable area
must also be created. Since t
This patch series provides support for running EDK2/OVMF under SEV-ES.
Secure Encrypted Virtualization - Encrypted State (SEV-ES) expands on the
SEV support to protect the guest register state from the hypervisor. See
"AMD64 Architecture Programmer's Manual Volume 2: System Programming",
section "
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
The GHCB is used by an SEV-ES guest for communicating between the guest
and the hypervisor. Create the GHCB definition as defined by the GHCB
protocol definition.
Cc: Michael D Kinney
Cc: Liming Gao
Signed-off-by: Tom Lendacky
---
MdePkg
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a CPUID intercept generates a #VC exception. VMGEXIT must be
used to allow the hypervisor to handle this intercept.
Add support to construct the required GHCB values to support a CPUID NAE
event. Additionally, CPUID 0x_000d
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
For SEV-ES, the GHCB page address is stored in the GHCB MSR register
(0xc0010130). Define the register and the format used for register
during GHCB protocol negotiation.
Cc: Michael D Kinney
Cc: Liming Gao
Signed-off-by: Tom Lendacky
---
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a NPF intercept for an NPT entry with a reserved bit set
generates a #VC exception. This condition is assumed to be an MMIO access.
VMGEXIT must be used to allow the hypervisor to handle this intercept.
Add support to construct
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
To support issuing a VMGEXIT instruction, create a library that can be
used to perform GHCB and VMGEXIT related operations and to issue the
actual VMGEXIT instruction when using the GHCB.
Additionally, two VMGEXIT / MMIO related functions ar
Hi Shindo-san,
Please see my feedback inline.
Thanks,
Nate
On Mon, Mar 02, 2020 at 08:40:42AM +, Shindo, Miki wrote:
> REF : https://bugzilla.tianocore.org/show_bug.cgi?id=2542
>
> ReportPreMemFv () has redundant calls to install Fsp FVs.
> FSP-M, S, U FVs do not need to be installed
> when
The series has been pushed as 852b889b~..068c6c48
-Original Message-
From: Agyeman, Prince
Sent: Tuesday, February 25, 2020 4:59 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L
Subject: [edk2-platforms] [PATCH 0/2] Add VS2017 Support
REF: https://bugzilla.tianocor
On 2/26/20 11:11 PM, Laszlo Ersek wrote:
Add a function that collects the APIC IDs of CPUs that have just been
hot-plugged, or are about to be hot-unplugged.
Pending events are only located and never cleared; QEMU's AML needs the
firmware to leave the status bits intact in the hotplug register b
On 02/26/20 23:11, Laszlo Ersek wrote:
> Supersedes: <20200223172537.28464-1-ler...@redhat.com>
> Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=1512
> Repo: https://github.com/lersek/edk2.git
> Branch: vcpu_hotplug_smm_bz_1512_v2
>
> V1 was posted at:
>
> * [edk2-devel] [PA
On 03/02/20 16:46, Boris Ostrovsky wrote:
> On Wed, Feb 26, 2020 at 05:12 PM, Laszlo Ersek wrote:
>
>>
>> Supersedes: <20200223172537.28464-1-ler...@redhat.com>
>> Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=1512
>> Repo: https://github.com/lersek/edk2.git
>> Branch: vcpu_hotplug_smm_
System will hang at debug print if enter RecordVarErrorFlag
in runtime.
This patch fix hang issue when run fwts in OS:
fwts uefirtmisc
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c | 18 ---
On Wed, Feb 26, 2020 at 05:12 PM, Laszlo Ersek wrote:
>
> Supersedes: <20200223172537.28464-1-ler...@redhat.com>
> Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=1512
> Repo: https://github.com/lersek/edk2.git
> Branch: vcpu_hotplug_smm_bz_1512_v2
>
> V1 was posted at:
>
> * [edk2-dev
When occur reclaim in AutoUpdateLangVariable(), the CurrPtr of Variable
is invalid. The State will be update with wrong position after
UpdateVariable in this situation and two valid PlatformLang or Lang
variables will exist. BmForEachVariable() will enter endless loop while
exist two valid Platform
There are two infrequent issues in variable.
Ming Huang (2):
MdeModulePkg/Variable: Remove some debug print for runtime
MdeModulePkg/Variable: Move FindVariable after AutoUpdateLangVariable
.../Universal/Variable/RuntimeDxe/Variable.c | 44 ++--
1 file changed, 21 ins
Points noted. Will look to avoid these in future patches.
Regards,
/Pete
On 2020.03.02 18:30, Ard Biesheuvel wrote:
On Mon, 2 Mar 2020 at 18:21, Pete Batard wrote:
From: Andrei Warkentin
Instead use ConfigDxe. This will allow selective loading/patching
to enable different SBBR/EBBR profil
On Mon, 2 Mar 2020 at 18:21, Pete Batard wrote:
>
> From: Andrei Warkentin
>
> Instead use ConfigDxe. This will allow selective loading/patching
> to enable different SBBR/EBBR profiles.
>
For future patches, please don't break sentences in between the title
and the commit log body. In my email
On Mon, 2 Mar 2020 at 18:40, Andrei Warkentin wrote:
>
> Hi Ard,
>
> > Do we really need this patch? For development, you can put anything
> > you want here. For doing releases, I'd expect edk2-platforms to be in
> > sync with edk2-non-osi, given that there are more blobs there than
> > TF-A, righ
On 03/02/20 08:29, Ard Biesheuvel wrote:
> On x86, the kernel image consists of a setup block and the actual kernel,
> and QEMU presents these as separate blobs, whereas on disk (and in terms
> of PE/COFF image signing), they consist of a single image.
>
> So add support to our FS loader driver to
Hi Ard,
> Do we really need this patch? For development, you can put anything
> you want here. For doing releases, I'd expect edk2-platforms to be in
> sync with edk2-non-osi, given that there are more blobs there than
> TF-A, right?
This is a developer productivity improvement that I've found to
Hi Liming,
thanks for your review!
Oh, I missed this, yes indeed, I can just include LockBoxNullLib and it works
on RISCV64, too.
So we can drop this patch, too.
Cheers,
Daniel
From: Gao, Liming
Sent: Monday, March 2, 2020 14:18
To: devel@edk2.groups.io ; Schaef
Hi Liming,
You're right, it doesn't make sense to define this PCD on other architectures
and it is not necessary.
I wrote this patch before patch 1 (MdeModulePkg: Restrict libraries using SMM
to x86).
With the other patch, this PCD is not used on other architectures, so *we can
drop this patch*
On 03/02/20 08:29, Ard Biesheuvel wrote:
> We have no need for exposing the kernel command line as a file,
> so remove support for that.
OK
> Since the remaining blobs (kernel
> and initrd) are typically much larger than a page, switch to
> the page based allocator for blobs at the same time.
No
On 03/02/20 08:29, Ard Biesheuvel wrote:
> Drop the QEMU loader file system implementation inside this library,
> and switch to the separate QemuLoadImageLib library and the associated
> driver to expose the kernel and initrd passed via the QEMU command line.
>
> Ref: https://bugzilla.tianocore.or
From: Andrei Warkentin
Instead use ConfigDxe. This will allow selective loading/patching
to enable different SBBR/EBBR profiles.
Signed-off-by: Pete Batard
---
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 10 ++
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf | 2 ++
Pl
On 03/02/20 08:29, Ard Biesheuvel wrote:
> Add the QEMU loader DXE driver and client library to the build for
> our QEMU targeted implementations in ArmVirtPkg.
>
> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2566
> Signed-off-by: Ard Biesheuvel
> ---
> ArmVirtPkg/ArmVirtQemu.dsc
On 03/02/20 08:29, Ard Biesheuvel wrote:
> Implement QemuLoadImageLib, and make it load the image provided by the
> QEMU_EFI_LOADER_FS_MEDIA_GUID/kernel device path that we implemented
> in a preceding patch in a separate DXE driver, using only the standard
> LoadImage and StartImage boot services.
*Reminder:* TianoCore Community Meeting - EMEA/NAMO
*When:* Thursday, 5 March 2020, 9:00am to 10:00am, (GMT-08:00) America/Los
Angeles
*Where:* https://bluejeans.com/889357567?src=join_info
View Event ( https://edk2.groups.io/g/devel/viewevent?eventid=621371 )
*Organizer:* Brian Richardson bri
On Mon, 2 Mar 2020 at 15:42, Pete Batard wrote:
>
> From: Andrei Warkentin
>
> For PFTF developers working on the firmware, being able to use a
> local TF-A build without extra extra copy operations ends up being
> very helpful.
>
> This can be accomplished via a TFA_BUILD_ARTIFACTS option passed
On Mon, 2 Mar 2020 at 15:42, Pete Batard wrote:
>
> From: Andrei Warkentin
>
> Back in RaspberryPiPkg (before upstream Pi 3) support, I wrote
> some extra code in PlatformBootManagerLib and BootGraphicsResourceTableDxe
> to clear out the logo/BGRT, so that Windows would always show its own
> logo
On 2020.03.02 14:22, Ard Biesheuvel wrote:
On Mon, 2 Mar 2020 at 14:09, Pete Batard wrote:
On 2020.03.02 03:08, Andrei Warkentin via Groups.Io wrote:
Back in RaspberryPiPkg (before upstream Pi 3) support, I wrote
some extra code in PlatformBootManagerLib and BootGraphicsResourceTableDxe
to cl
As requested due to mangling, this is an unmodified resend of the 2 previous
patches:
* https://edk2.groups.io/g/devel/message/55159
* https://edk2.groups.io/g/devel/message/55160
Andrei Warkentin (2):
Platform/RPi4: allow overriding TF-A binaries during build
Platform/RPi4/Library/PlatformBo
From: Andrei Warkentin
Back in RaspberryPiPkg (before upstream Pi 3) support, I wrote
some extra code in PlatformBootManagerLib and BootGraphicsResourceTableDxe
to clear out the logo/BGRT, so that Windows would always show its own
logo instead of the platform logo. It kind of made sense back in t
From: Andrei Warkentin
For PFTF developers working on the firmware, being able to use a
local TF-A build without extra extra copy operations ends up being
very helpful.
This can be accomplished via a TFA_BUILD_ARTIFACTS option passed
to the edk2 build tool.
If/when the Pi 3 and 4 DSC/FDFs becom
On Mon, 2 Mar 2020 at 14:09, Pete Batard wrote:
>
> On 2020.03.02 03:08, Andrei Warkentin via Groups.Io wrote:
> > Back in RaspberryPiPkg (before upstream Pi 3) support, I wrote
> > some extra code in PlatformBootManagerLib and BootGraphicsResourceTableDxe
> > to clear out the logo/BGRT, so that W
On Wed, 26 Feb 2020 at 23:12, Laszlo Ersek wrote:
>
> During normal boot, CpuS3DataDxe allocates
>
> - an empty CPU_REGISTER_TABLE entry in the
> "ACPI_CPU_DATA.PreSmmInitRegisterTable" array, and
>
> - an empty CPU_REGISTER_TABLE entry in the "ACPI_CPU_DATA.RegisterTable"
> array,
>
> for eve
On 03/02/20 08:29, Ard Biesheuvel wrote:
> Introduce the QemuLoadImageLib library class that we will instantiate
> to load the kernel image passed via the QEMU command line using the
> standard LoadImage boot service.
>
> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2566
> Signed-off-by: Ar
On Wed, 26 Feb 2020 at 23:12, Laszlo Ersek wrote:
>
> Sort the [Packages], [LibraryClasses], and [Pcd] sections in the INF file.
> Pad the usage notes (CONSUMES, PRODUCES) in the [Pcd] section.
>
> Sort the Library #includes in the C file.
>
> This patch is functionally a no-op.
>
> Cc: Ard Bieshe
On Wed, 26 Feb 2020 at 23:12, Laszlo Ersek wrote:
>
> The @file comments in UefiCpuPkg/CpuS3DataDxe say,
>
> [...] It also only supports the number of CPUs reported by the MP
> Services Protocol, so this module does not support hot plug CPUs. This
> module can be copied into a CPU specific
On Wed, 26 Feb 2020 at 23:12, Laszlo Ersek wrote:
>
> With the help of the Post-SMM Pen and the SMBASE relocation functions
> added in the previous patches, we can now complete the root MMI handler
> for CPU hotplug.
>
> In the driver's entry point function:
>
> - allocate the pen (in a reserved p
On Wed, 26 Feb 2020 at 23:12, Laszlo Ersek wrote:
>
> Implement the First SMI Handler for hot-added CPUs, in NASM.
>
> Add the interfacing C-language function that the SMM Monarch calls. This
> function launches and coordinates SMBASE relocation for a hot-added CPU.
>
> Cc: Ard Biesheuvel
> Cc: I
On Wed, 26 Feb 2020 at 23:12, Laszlo Ersek wrote:
>
> Once a hot-added CPU finishes the SMBASE relocation, we need to pen it in
> a HLT loop. Add the NASM implementation (with just a handful of
> instructions, but much documentation), and some C language helper
> functions.
>
> Cc: Ard Biesheuvel
On Wed, 26 Feb 2020 at 23:12, Laszlo Ersek wrote:
>
> Call QemuCpuhpCollectApicIds() in the root MMI handler. The APIC IDs of
> the hotplugged CPUs will be used for several purposes in subsequent
> patches.
>
> For calling QemuCpuhpCollectApicIds(), pre-allocate both of its output
> arrays "Plugge
On Wed, 26 Feb 2020 at 23:12, Laszlo Ersek wrote:
>
> Add a function that collects the APIC IDs of CPUs that have just been
> hot-plugged, or are about to be hot-unplugged.
>
> Pending events are only located and never cleared; QEMU's AML needs the
> firmware to leave the status bits intact in the
On 2/26/20 11:11 PM, Laszlo Ersek wrote:
Clone the Null instance of SmmCpuPlatformHookLib from UefiCpuPkg to
OvmfPkg. In this patch, customize the lib instance only with the following
no-op steps:
- Replace Null/NULL references in filenames and comments with Qemu/QEMU
references.
- Update cop
On 2/26/20 11:11 PM, Laszlo Ersek wrote:
In the CoreStartImage() function [MdeModulePkg/Core/Dxe/Image/Image.c], if
the image entry point returns a failure code, then the DXE Core logs a
helpful DEBUG_ERROR message, with the following format string:
"Error: Image at %11p start failed: %r\n"
On Wed, 26 Feb 2020 at 23:12, Laszlo Ersek wrote:
>
> QEMU commit 3a61c8db9d25 ("acpi: cpuhp: add CPHP_GET_CPU_ID_CMD command",
> 2020-01-22) introduced a new command in the modern CPU hotplug register
> block that lets the firmware query the arch-specific IDs (on IA32/X64: the
> APIC IDs) of CPUs
On 2/26/20 11:11 PM, Laszlo Ersek wrote:
The @file comments in UefiCpuPkg/CpuS3DataDxe say,
[...] It also only supports the number of CPUs reported by the MP
Services Protocol, so this module does not support hot plug CPUs. This
module can be copied into a CPU specific package and cust
On Wed, 26 Feb 2020 at 23:12, Laszlo Ersek wrote:
>
> Add a handful of simple functions for accessing QEMU's hotplug registers
> more conveniently. These functions thinly wrap some of the registers
> described in "docs/specs/acpi_cpu_hotplug.txt" in the QEMU tree. The
> functions hang (by design)
On 03/02/20 08:29, Ard Biesheuvel wrote:
> Expose the existing implementation of an abstract filesystem exposing
> the blobs passed to QEMU via the command line via a standalone DXE
> driver.
"git show --find-copies-harder" works wonders while reviewing this patch :)
>
> Notable difference with
On Wed, 26 Feb 2020 at 23:12, Laszlo Ersek wrote:
>
> Add a new SMM driver skeleton that registers a root SMI handler, and
> checks if the SMI control value (written to 0xB2) indicates a CPU hotplug
> SMI.
>
> QEMU's ACPI payload will cause the OS to raise a broadcast SMI when a CPU
> hotplug even
Maciej:
Thanks for your analysis. I agree with you. This change is not necessary to
catch edk2 stable tag 202002.
Thanks
Liming
> -Original Message-
> From: Rabeda, Maciej
> Sent: Friday, February 28, 2020 8:35 PM
> To: Gao, Liming ; devel@edk2.groups.io; Laszlo Ersek
> ; Kinney, Mich
Daniel:
I agree this fix. But, I don't meet with this failure with GCC on IA32/X64
arch. So, I don't fix it early. Reviewed-by: Liming Gao
Thanks
Liming
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Daniel Schaefer
> Sent: Monday, March 2, 2020 6:33 PM
> To: devel@edk
1 - 100 of 139 matches
Mail list logo
