Thanks for locating the bug @c! Is there any way to modify this in HLS
instead of modifying the generated Verilog, so that more people could avoid the
pitfall?
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What about modifying finsh instruction to write a bool into a piece of shared
memory? By this way, cpu can clear it after reading.
@liangfu
Clear On Read in register is the definately efficient way. But if hls
programming cannot easily achieve this aim. Clear On Read in shared memory
might be
While adding an operator in Topi, most of the time we need to put certain
checks on dynamic input data values for which values are known at runtime only.
Is there a way in the form of tensor expression, to assert values in compute
definition?
For ex. An operator accepts indices as dynamic in
if you are using hybrid script, I am sure that there is an assert statement
that you may be interested. CC: @were
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New `MergeComposite` pass PR filed.
https://github.com/apache/incubator-tvm/pull/5656
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Hi all,
We have completed a workable draft of bfloat16 (bf16) in TVM and the bf16
related codegen in LLVM.
We add bfloat16 as a new type named "bf16" in the frontend. Completed LLVM
backend for generating bf16.
* Use int16 as the storage type in LLVM
* Add legalization to enable computation
@tqchen As you have proposed to eliminate "bfloat16" dtype after the
legalization pass, I have two concerns.
* The legalization pass will be more compilicated. It has to check every TIR
node to replace the bf16 dtype
* As the casting between bf16 and fp32 will be lowered as function calls as
