Thanks @merrymercy, this is really awesome work. I second Jared's comment on
work involved in adding a backend. I'd be happy to chat some more about how one
would add automated compilation to different hardware accelerators including
VTA.
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@jroesch Currently, it is about 500 loc per backend. I am working on
improvements so it may increase.
@yzhliu
* simple reduction: reduction ops that do not have reuse opportunity (e.g.
softmax, argmin)
* complex reduction: reduction ops that have reuse opportunity (e.g. matmul,
conv2d
* direct
# TVM Monthly - March 2019
https://discuss.tvm.ai/t/tvm-monthly-march-2019/2083
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@merrymercy I'm less interested in LOC and more how much conceptual burden
there is. What are the key pieces that make up a backend description is more my
question.
I looked over the code but was at SysML and have two deadlines this week so I
haven't had a chance to really look it over. Look f
Open sourced: https://github.com/tensorflow/mlir
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@merrymercy Auto-scheduler will create another search space consists of
schedule templates. For a given set of hardware parameters, it will try various
schedule templates and for each template do some auto-tuning on real device.
This means for each minor device type, we need to do all these step
@merrymercy Do you think this analysis design can be easily extended to be
working based on TVM Tensor AST (HalideIR) instead of ScheduleStage? Not urgent
but I think eventually we will make schedule primitives work on HalideIR, so
that we can unify the underlying data structure of schedule and
Good discussions, I think in general we can move to summarize the common
patterns and make things work for specific hardware backend. As for point
bought by @yzhliu (unifying schedule with pass), eventually ScheduleStage
itself(or other IR structure) can be viewed as a dialect of the IR, and we
