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ring buffer optimization is common and critical on dsp(or other VLIW-like
Asic). Except tvm framwork can support this.
https://discuss.tvm.ai/t/questions-about-memory-latency-hiding-on-dsp/1843
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Topic](https://discuss.tvm.ai/t/tensor-expression-add-hardware-specific-schedule/18
@yzhliu You are right. At that time, we thought `AlterOpLayout` does not have
dependency problem and can be done in a single forward pass, so we tried to do
a lot of things in a single pass, which includes operator substitution, layout
inference, and layout-transformation insertion. I agree t
