ring buffer optimization is common and critical on dsp(or other VLIW-like
Asic). Except tvm framwork can support this.
https://discuss.tvm.ai/t/questions-about-memory-latency-hiding-on-dsp/1843
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I am not sure if we could summarize a global machine IR, but we do intend to
make VTA a class of accelerators so TVM stack can be used to target any
accelerators people might built. @thierry might has more thoughts on this
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