Sure. Thanks for including me in the doc! Glad to help.
I can send you the raw file for the IterVar diagram which can be edited with
http://draw.io, if you want it.
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@YuanLin thanks for the detailed comments! My replies are below.
**Suggested change 1**
I agree that the hyper-graph (edges connecting more than two nodes) concept
isn't necessary. I picked that up from a comment in
[schedule.h](https://github.com/dmlc/tvm/blob/master/include/tvm/schedule.h#
Thanks Tianqi. I'll rewrite that section to emphasize the benefit to
extensibility, of having a separate IntSet.
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Great! Thanks for your encouragement. I look foward to hearing your detailed
comments when you get a chance.
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Okay, it's been two weeks on this RFC, so I'm going to prepare a pros/cons
summary of the discussion so far in preparation for further action.
Regarding the proposal to **replace SGX support in TVM with Fortanix**:
**Pros**
* tightly integrated into Rust ecosystem, which gives support for more
+1
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@jdavies-huawei Thanks for creating this document. This is great. I just went
through the same exercise so to understand the InferBound and my notes are not
nearly as comprehensive as yours.
Following are some diffs, which I hope shall be useful to you.
### Suggested change 1
The following
is it there yet, is it there yet.
Can't wait to try that out.
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I propose two changes to instructions.
- `AllocTensor` uses shape stored in the register instead of hardcode shape in
the instruction. This can help support dynamic shape in VM in the future. We
can store constant shapes in the constant lists, and use `LoadConst` to load
them.
- Change `Phi` to
There is an active effort (RFC to be released soon by @vegaluis) on providing
cycle accurate simulation of the VTA hardware design. For now, we provide
software emulation libraries that are open sourced, but don't provide a cycle
accurate accounting of what goes on within the chip. The benefit
Is the architecture simulation environment open?We want to explore other
architectures based on vta.
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+1
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