Just a thought
On M7 devices, the DMA buffers need to be cache line aligned. Nuttx has
special malloc functions configurable for FAT buffers.
Also, I'm not sure the cache invalidate code was tested well for
store-into cache mode. Store-through was known to be working.
-Bob
On Fri, Sep 18, 2
.
Regards,
Bob
On 9/18/2020 8:54 AM, Bob Feretich wrote:
Just a thought
On M7 devices, the DMA buffers need to be cache line aligned. Nuttx
has special malloc functions configurable for FAT buffers.
Also, I'm not sure the cache invalidate code was tested well for
store-into cache
To debug this type of problem you need to be able to observe the
activity on the SPI bus.
A 4-channel scope would be ideal, but you can do it with a 2-channel scope.
Most likely, you are not routing your "SPI chip select" to the
appropriate GPIO pin. That could be caused by several factors.
I have tried to write a nsh script that...
* Runs an application.
* Examines the application's return code.
* Then runs one of several applications based upon the value of the return code.
The application return code seems to have an effect on $?, if I set the return
code to 0 or 1,
but if I set
